On implementability of Polymorphic Register Files

Abstract

Abstract-This paper studies the implementability of performance efficient multi-lane Polymorphic Register Files (PRFs). Our PRF implementation uses a 2D array of p × q linearly addressable memory banks, with customized addressing functions to avoid address routing circuits. We target one single-view and a set of four non redundant multi-view parallel memory schemes that cover all widely used access patterns in scientific and multimedia applications: 1) p × q rectangle, p · q row, p · q main and secondary diagonals; 2) p × q rectangle, p · q column, p · q main and secondary diagonals; 3) p · q row, p · q column, aligned p × q rectangle; 4) p × q, q × p rectangles (transposition). Reconfigurable hardware was chosen for the implementation due to its potential in enhancing the PRF runtime adaptability. For a proof of concept, we prototyped a 2 read, 1 write ports PRF on a Virtex-7 XC7VX1140T-2 FPGA. We consider four sizes for the 16 lanes PRFs -16 × 16, 32 × 32, 64 × 64 and 128 × 128 and three multi-lane configurations, 8, 16 and 32, for the 128 × 128 PRF. Synthesis results suggest clock frequencies between 111 MHz and 326 MHz while utilizing less than 10% of the available LUTs. By using customized addressing functions, the LUT usage is reduced by up to 29% and the clock frequency is up to 77% higher compared to a straight-forward implementation.

Scalability Study of Polymorphic Register Files

“…Moreover, a similar performance level could be achieved by fewer PRF instances than the cores needed in a Cell BE-based system, potentially saving area and power [5]. An FPGA implementation, prototyped in [6], can adjust additional PRF parameters during runtime (e.g., total storage size, number of lanes and ports), at the expense of lower clock frequency compared to the ASIC version presented here.…”

“…We consider five parallel access schemes suitable for the implementation of the PRF: the single-view Rectangle Only (ReO) scheme, which supports conflict free accesses shaped as p×q rectangles, suggested in [11], and a set of four multi-view schemes, supporting conflict free access to the most common vector operations for scientific and multimedia applications, also used in [6]: 1) Rectangle Row (ReRo): p × q rectangle, …”

“…For all the schemes considered, the standard linear address assignment function [6] can be customized for accessing blocks of p · q elements. In this case, the coordinates (i, j) refer to the upper left corner of the accessed block:…”

“…For the standard, non-customized addressing function, c i = c j = 0. Their complete mathematical definitions are provided in [11] and in [6].…”

“…DESIGN UNDER STUDY The block diagram of an 8 vector lanes PRF hardware implementation, first proposed in [6], is depicted in Fig. 2 (SPR not shown).…”