Scalability Study of Polymorphic Register Files

Abstract

Abstract-We study the scalability of multi-lane 2D Polymorphic Register Files (PRFs) in terms of clock cycle time, chip area and power consumption. We assume an implementation which stores data in a 2D array of linearly addressable memory banks, and consider one single-view and four suitable multi-view parallel access schemes which cover all basic access patterns commonly used in scientific and multimedia applications. The PRF design features 2 read and 1 write ports, targeting the TSMC 90nm ASIC technology. We consider three PRF sizes -32KB, 128KB and 512KB and four multi-lane configurations -8 / 16 / 32 and 64 lanes. Synthesis results suggest that the clock frequency varies between 500MHz for a 512KB PRF with 64 vector lanes and 970Mhz for a 32KB / 8-lanes case. Estimated power consumption ranges from less than 300mW (dynamic) and 10mW (leakage) for our 8-lane, 32KB PRF up to 8.7W (dynamic) and 276mW (leakage) for a 512KB with 64 lanes. We also show the correlation among the storage capacity, the number of lanes, and the chip overall area. Furthermore, we also investigated customized addressing functions. Our experimental results suggest up to 21% increase of the clock frequency, and up to 39% combinational hardware area reduction (nearly 10% of the total area) compared to our straightforward implementations. Concerning power, we reduce dynamic power with up to 31% and leakage with nearly 24%.

The Case for Polymorphic Registers in Dataflow Computing

“…The C2050 features a total of 448 SIMD lanes running at 1.15 GHz. This clock frequency is comparable to our ASIC synthesis results for the PRF [35]. Therefore, we express the throughput for both the PRF and the NVIDIA C2050 in terms of pixels/1000 cycles.…”

“…When targeting a 90 nm ASIC technology, the PRF clock frequency is between 500 and 970 MHz for storage sizes of up to 512 KB and up to 64 vector lanes. Power consumption remains reasonable, not exceeding 8.7 W and 276 mW for dynamic and static power, respectively [10].…”

“…Synthesis results for FPGA and ASIC technologies have been presented in [5,9] and [10]. Specifically, results targeting the Virtex-7 XC7VX1140T-2 FPGA show feasible clock frequencies between 111 and 326 MHz and reasonable logic resources usage (less than 10 and 15% of the available LUTs and BRAMs, respectively).…”

Dataflow computing with Polymorphic Registers

“…Moreover, MaxCompiler allows instantiation of hand crafted HDL code, which connects to other Kernels via streams. We take advantage of this to instantiate our PRF hardware, described in detail in [6] and [7].…”

“…Synthesis results for FPGA and ASIC technologies have been presented in [7], [6] and [5]. Results targeting the Virtex-7 XC7VX1140T-2 FPGA show feasible clock frequencies between 111 MHz and 326 MHz and reasonable logic resources usage (less than 10% of the available LUTs).…”