On Determining the Real Output Xs by SAT-Based Reasoning

Elm, Melanie; Kochte, Michael A.; Wunderlich, Hans-Joachim

doi:10.1109/ats.2010.16

Cited by 6 publications

(4 citation statements)

References 23 publications

(27 reference statements)

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“…Conventional SAT solvers [27], [28] used as the vital part of most of SAT-based ATPG tools produce completely specified solutions (all variables are assigned a value in the satisfying solution), which somewhat restricts the search for subsequent test patterns. Although there are many techniques allowing don't cares in the solution [29], [30], or there are even optimization SAT solvers maximizing the number of don't cares in the solution [31]- [35] (let us call them DC-SAT solvers), we will show that they are highly unsuitable for our application.…”

Section: Dedicated Design-for-testability (Dft) Architecturesmentioning

confidence: 93%

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Simulation and SAT Based ATPG for Compressed Test Generation

Balcarek

Fier

Schmidt

2013

2013 Euromicro Conference on Digital System Design

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Abstract-This paper presents a novel ATPG algorithm directly producing compressed test patterns. It benefits both from the features of satisfiability-based techniques and symbolic simulation. The ATPG is targeted to architectures comprised of interconnected embedded cores, particularly to the RESPIN architecture. We show experimentally that the proposed ATPG significantly outperforms the state-of-the-art approaches in terms of the test compression ratio.

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Section: Dedicated Design-for-testability (Dft) Architecturesmentioning

confidence: 93%

“…Consequently, this also compromises using DC-SAT solvers ( [29]- [35]) to obtain don't cares; don't cares must be injected with care, and definitely their number in the SAT solution must not be the optimization criterion for the SAT-solver. …”

Section: Cpdcimentioning

confidence: 99%

Simulation and SAT Based ATPG for Compressed Test Generation

Balcarek

Fier

Schmidt

2013

2013 Euromicro Conference on Digital System Design

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“…The accurate computation of signal states in a circuit in presence of X-values can be achieved by formal reasoning for register-transfer and gate level simulation [19][20][21]. The methods used rely on symbolic computation by Boolean satisfiability (SAT), quantified Boolean formula (QBF) reasoning, or binary decision diagrams (BDDs).…”

Section: Unknown Values In Circuit Testmentioning

confidence: 99%

Modeling Unknown Values in Test and Verification

Becker

Sauer

Scholl

et al. 2015

Formal Modeling and Verification of Cyber-Physical Systems

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Abstract.With increasing complexities and a component-based design style the handling of unknown values (e. g., at the interface of components) becomes more and more important in electronic design automation (EDA) and production processes. Tools are required that allow an accurate modeling of unknowns in combination with algorithms balancing exactness of representation and efficiency of calculation. In the following, state-ofthe-art approaches are described that enable an efficient and successful handling of unknown values using formal techniques in the areas of Test and Verification.

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“…The accurate computation of signal states in a circuit in presence of X-values can be achieved by formal reasoning for register-transfer and gate level simulation [16], [17], [18]. These methods employ symbolic computations by Boolean satisfiability (SAT), Quantified Boolean Formula (QBF) reasoning [19], or Binary Decision Diagrams (BDDs).…”

Section: Introductionmentioning

confidence: 99%

Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values

Erb

Kochte

Reimer

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Unknown (X) values emerge during the design process as well as during system operation and test application. X-sources are for instance black boxes in design models, clockdomain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements.To compute a test pattern for a given fault, well-defined logic values are required both for fault activation and propagation to observing outputs. In presence of X-values, conventional test generation algorithms, based on structural algorithms, Boolean satisfiability (SAT), or BDD-based reasoning may fail to generate test patterns or to prove faults untestable.This work proposes the first efficient stuck-at and transitiondelay fault test generation algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal pessimism of conventional algorithms when X-values are considered by mapping the test generation problem to the satisfiability of Quantified Boolean Formulae (QBF).Experiments on ISCAS benchmarks and larger industrial circuits investigate the increase in fault coverage for conventional deterministic and potential detection requirements for both randomized and clustered X-sources.

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On Determining the Real Output Xs by SAT-Based Reasoning

Cited by 6 publications

References 23 publications

Simulation and SAT Based ATPG for Compressed Test Generation

Simulation and SAT Based ATPG for Compressed Test Generation

Modeling Unknown Values in Test and Verification

Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values

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