Simulation and SAT Based ATPG for Compressed Test Generation

Abstract

Abstract-This paper presents a novel ATPG algorithm directly producing compressed test patterns. It benefits both from the features of satisfiability-based techniques and symbolic simulation. The ATPG is targeted to architectures comprised of interconnected embedded cores, particularly to the RESPIN architecture. We show experimentally that the proposed ATPG significantly outperforms the state-of-the-art approaches in terms of the test compression ratio.

PBO-Based Test Compression

“…Only smaller circuits were chosen for a thorough testing of the algorithms properties. Since the results greatly resemble results from [20], we refer to this paper for results of bigger circuits.…”

“…Specifying additional values generally decreases the chance for overlapping, but increases the number of covered faults. We have shown in [20] that this issue is crucial -when the local fault coverage is lost, the compression process is prolonged and the resulting bitstream is bigger too.…”

“…Lines 6 to 16 are the main phase, which adds terms describing the behavior of undefined values to the function. Finally, the third phase (line 18) encodes the table and phase four (19)(20)(21)(22)(23)(24)(25)(26)(27) outputs the resulting CNF, using CNF and DNF duality.…”

“…As our previous results indicated, blindly introduced unspecified values can do more harm than good [20]. Therefore, similarly to [20], we combine the PBO technique with fault simulation.…”

“…Therefore, similarly to [20], we combine the PBO technique with fault simulation. In this process, the PBO generates test vectors with maximum of unspecified bits, which are subsequently assigned a value, so that the fault coverage is maximized.…”