On-chip Jitter Measurement Using Vernier Ring Time-to-Digital Converter

Abstract

This paper presents an on-chip jitter measurement technique based on the Vernier ring time-do-digital converter (VRTDC). Vernier delay line is an attractive structure for the implementation of high performance TDC due to its sub-gatedelay resolution and cancellation of the first order process, voltage and temperature (PVT) variations. In order to improve the detectable range, area cost and power consumption of the conventional Vernier delay line TDC, the Vernier ring structure is developed to place two delay lines and comparator chains in ring format for the reuse of hardware, which enables the VR-TDC to achieve a fine resolution without sacrificing detectable range. The build-in coarse and fine interpolations reduce the power and area. This on-chip jitter measurement scheme can measure a large jitter with a fine resolution smaller than 8ps. An exemplary jitter test is given in this paper to demonstrate the capability of the proposed jitter measurement scheme.

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

“…A time-to-digital converter has been used for measuring delay and clock jitter [10]- [13]. We have designed a boundary scan cell that has a capability to test the delay of incoming transitions from another core or chip [14].…”

“…Some other methods have been proposed to use the embedded sensors for measuring the circuit delay [8], [9]. Time-to-digital converters are also utilized for measuring the circuit delay or clock jitter [10]- [13].…”

A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing

“…In case of a rising transition, there exists such that the captured values are 1 at from 0 to −1 and 0 at to . To measure the delay more precisely, Vernier delay line TDC that has two delay lines is utilized [11]- [14]. However, in our method a simple TDC like Fig.…”

“…DELAY FAULT DETECTION USING TIME-TO-DIGITAL CONVERTER A time-to-digital converter is utilized for measuring delay or jitter [11]- [14]. Figure 1 shows an example of a time-todigital converter (TDC) used in our design.…”

“…Several methods have been proposed to measure the delay using time-to-digital converters as on-chip jitter measurement circuits [11]. In [12]- [14], delay measurement circuit using time-to-digital converter has been proposed.…”