A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing

Yotsuyanagi, Hiroyuki; Makimoto, Hiroyuki; Hashizume, Masaki

doi:10.1109/ats.2011.63

Cited by 5 publications

(7 citation statements)

References 14 publications

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“…We have designed a boundary scan cell that has a capability to test the delay of incoming transitions from another core or chip [14]. The boundary scan cells can form a time-to-digital converter that is utilized for detecting delay.…”

Section: Delay Detection Using Scan Cells With Time-todigital Convertermentioning

confidence: 99%

“…Copyright c 2013 The Institute of Electronics, Information and Communication Engineers This TDC circuit is modified from that of [14], [15]. In the previous design, the initial logic value at the output of each XOR gate can be set only to 0.…”

Section: Delay Detection Using Scan Cells With Time-todigital Convertermentioning

confidence: 99%

“…In our testable design, a boundary scan cell is modified such that the cells can form a TDC that is utilized for detecting delay [14], [15]. Figure 3 shows a basic boundary scan cell [16].…”

Section: Modified Boundary Scan Cell To Embed a Time-todigital Convertermentioning

confidence: 99%

“…We have proposed the boundary scan circuit in which a time-to-digital converter can be embedded for estimating the delay of an incoming transition [14], [15]. In our method, incoming transitions from the other cores or chips is delayed by some gates.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

Yotsuyanagi

Makimoto

Nimiya

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper proposes a method for testing delay faults using a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC.

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Section: Delay Detection Using Scan Cells With Time-todigital Convertermentioning

confidence: 99%

Section: Delay Detection Using Scan Cells With Time-todigital Convertermentioning

confidence: 99%

Section: Modified Boundary Scan Cell To Embed a Time-todigital Convertermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

Yotsuyanagi

Makimoto

Nimiya

et al. 2013

IEICE Trans. Inf. & Syst.

Self Cite

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“…High-resolution delay measurement capability can be achieved by using this method. The paper [10] presented modified boundary scan cells in which a time-to-digital converter (TDC) is embedded. Tsai et al proposed a built-in delay measurement (BIDM) circuit consisting of coarse and fine blocks, which is an extension of the modified VDL technique.…”

Section: Related Workmentioning

confidence: 99%

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

Zhang

Namba

Ito

2014

IEICE Trans. Inf. & Syst.

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SUMMARYWith IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.

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An Area Efficient Wide Range On-Chip Delay Measurement Architecture

Krishnamurthy

Sharma

2013

Communications in Computer and Information Science

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A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing

Cited by 5 publications

References 14 publications

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

An Area Efficient Wide Range On-Chip Delay Measurement Architecture

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