On-chip Face Recognition System Design with Memristive Hierarchical Temporal Memory

IEEE Trans. Neural Netw. Learning Syst.

Chua

2020

Self Cite

218

126

The volume, veracity, variability and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing.

Section: Neuromorphic Architectures a Neural Network Architecturesmentioning

confidence: 99%

Neuromemristive Circuits for Edge Computing: A Review

IEEE Trans. Neural Netw. Learning Syst.

Chua

2020

Self Cite

218

126

“…3) Memristive HTM System: The analog implementation of the overall HTM system for face recognition is proposed in [25]. The system involves the input data controller, HTM SP, HTM TM, output data controller and pattern matcher.…”

Section: B Analog Implementationmentioning

confidence: 99%

“…4) Memristor Logic Circuit for Analog SP and Analog TM: Recent research illustrated the modified implementation of the analog HTM SP and analog hardware design of the HTM TM [12]. Comparing to the previous works [10], [11], [25], the modified HTM SP analog circuit level implementation is more scalable and introduces randomization process, which is more accurate and closer to the original HTM SP algorithm. The overall modified HTM SP architecture is illustrated in Fig.…”

Section: B Analog Implementationmentioning

confidence: 99%

“…In all HTM implementations [12], [30], [13], [11], [10], [25], the HTM weights are programmed as particular resistive states of the memristor. As the memristor is a device that can exhibit various resistive states between R ON and R OF F and possesses a non-volatility property, it can be programmed applying a pulse of a certain duration and amplitude across the memristor.…”

Section: Weight Update Processmentioning

confidence: 99%

“…For example, the parameters of HTM for NPL related problems [16] are different from the image classification problems [12], [11]. In research works [12], [25] and [11], the authors select the number of columns and number of regions experimentally performing system level simulations in Matlab simulations and verifying the best possible accuracy for particular applications and databases. In addition, even for the same application the number of columns can vary for different databases, and the optimum parameter for particular application can be selected based on experimental verification of the maximum possible accuracy for all databases [12].…”

Section: Applications Of Memristive Htmmentioning

confidence: 99%

See 2 more Smart Citations

Hierarchical Temporal Memory Using Memristor Networks: A Survey

Dolzhikova

IEEE Trans. Emerg. Top. Comput. Intell.

2018

Self Cite

This paper presents a survey of the currently available hardware designs for implementation of the human cortex inspired algorithm, Hierarchical Temporal Memory (HTM). In this review, we focus on the state of the art advances of memristive HTM implementation and related HTM applications. With the advent of edge computing, HTM can be a potential algorithm to implement on-chip near sensor data processing. The comparison of analog memristive circuit implementations with the digital and mixed-signal solutions are provided. The advantages of memristive HTM over digital implementations against performance metrics such as processing speed, reduced on-chip area and power dissipation are discussed. The limitations and open problems concerning the memristive HTM, such as the design scalability, sneak currents, leakage, parasitic effects, lack of the analog learning circuits implementations and unreliability of the memristive devices integrated with CMOS circuits are also discussed.

Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Salama

IEEE Trans. Circuits Syst. I

2019

Self Cite

121

The on-chip implementation of learning algorithms would speed-up the training of neural networks in crossbar arrays. The circuit level design and implementation of backpropagation algorithm using gradient descent operation for neural network architectures is an open problem. In this paper, we proposed the analog backpropagation learning circuits for various memristive learning architectures, such as Deep Neural Network (DNN), Binary Neural Network (BNN), Multiple Neural Network (MNN), Hierarchical Temporal Memory (HTM) and Long-Short Term Memory (LSTM). The circuit design and verification is done using TSMC 180nm CMOS process models, and TiO2 based memristor models. The application level validations of the system are done using XOR problem, MNIST character and Yale face image databases.