Hierarchical Temporal Memory Using Memristor Networks: A Survey

Krestinskaya, Olga; Dolzhikova, Irina; James, Alex Pappachen

doi:10.1109/tetci.2018.2838124

Cited by 31 publications

(21 citation statements)

References 38 publications

(129 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This is compatible with a state dependent parameter α, rather than a constant (see Figure 1 of [34]). A survey of recent hardware designs for temporal memory is provided in [106].…”

Section: Volatility: Autonomous Plasticitymentioning

confidence: 99%

Memristors for the Curious Outsiders

Caravelli

Carbajal

2018

Technologies

View full text Add to dashboard Cite

We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2-terminal passive component with a dynamic resistance depending on an internal parameter. We provide an brief historical introduction, as well as an overview over the physical mechanism that lead to memristive behavior. This review is meant to guide nonpractitioners in the field of memristive circuits and their connection to machine learning and neural computation.

show abstract

“…This is compatible with a state dependent parameter α, rather than a constant (see Figure 1 of [34]). A survey of recent hardware designs for temporal memory is provided in [106].…”

Section: Volatility: Autonomous Plasticitymentioning

confidence: 99%

Memristors for the Curious Outsiders

Caravelli

Carbajal

2018

Technologies

View full text Add to dashboard Cite

show abstract

“…As the current memristor technology is unstable and memristors can have switching problems, the selection of memristive devices for this architecture is important, and the effect of the non-ideal behavior of real memristive devices should be studied. The current memristive technology allows the implementation of binary states [13], however the endurance issues, effects of switching probability of the accuracy [14] and other aspect of non-ideal behaviour of memristive devices should be studied.…”

Section: Discussionmentioning

confidence: 99%

Binary Weighted Memristive Analog Deep Neural Network for Near-Sensor Edge Processing

Krestinskaya

James

2018

2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO)

View full text Add to dashboard Cite

The memristive crossbar aims to implement analog weighted neural network, however, the realistic implementation of such crossbar arrays is not possible due to limited switching states of memristive devices. In this work, we propose the design of an analog deep neural network with binary weight update through backpropagation algorithm using binary state memristive devices. We show that such networks can be successfully used for image processing task and has the advantage of lower power consumption and small on-chip area in comparison with digital counterparts. The proposed network was benchmarked for MNIST handwritten digits recognition achieving an accuracy of approximately 90%.

show abstract

“…HTM architecture is hierarchical and modular, and it enables sparse processing of information. HTM is divided into two parts: (1) Spatial Pooler (SP) and (2) Temporal Memory (TM) [34], [35]. The main purpose of the HTM SP is to encode the input data and produce its sparse distributed representation that finds application in various data classification problems.…”

Section: Background a Learning Algorithms And Biologically Inspimentioning

confidence: 99%

Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Krestinskaya

Salama

James

2019

IEEE Trans. Circuits Syst. I

Self Cite

123

View full text Add to dashboard Cite

The on-chip implementation of learning algorithms would speed-up the training of neural networks in crossbar arrays. The circuit level design and implementation of backpropagation algorithm using gradient descent operation for neural network architectures is an open problem. In this paper, we proposed the analog backpropagation learning circuits for various memristive learning architectures, such as Deep Neural Network (DNN), Binary Neural Network (BNN), Multiple Neural Network (MNN), Hierarchical Temporal Memory (HTM) and Long-Short Term Memory (LSTM). The circuit design and verification is done using TSMC 180nm CMOS process models, and TiO2 based memristor models. The application level validations of the system are done using XOR problem, MNIST character and Yale face image databases.

show abstract

Hierarchical Temporal Memory Using Memristor Networks: A Survey

Cited by 31 publications

References 38 publications

Memristors for the Curious Outsiders

Memristors for the Curious Outsiders

Binary Weighted Memristive Analog Deep Neural Network for Near-Sensor Edge Processing

Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Contact Info

Product

Resources

About