On calculating efficient LFSR seeds for built-in self test

Fagot, C.; Gascuel, Olivier; Girard, Patrick; Landrault, C.

doi:10.1109/etw.1999.803819

Cited by 43 publications

(11 citation statements)

References 16 publications

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“…Moreover, mixed-mode BIST is related to a specific fault model. Pseudo-random BIST consists in applying test patterns that exhibit randomness but which are generated using special-purpose hardware (LFSR or Cellular Automata) and are thus repeatable [9,10,11]. Pseudo-random BIST is the least hardware consuming solution but requires test lengths which may be long in some cases.…”

Section: Introductionmentioning

confidence: 99%

Random Adjacent Sequences

David

Girard

Landrault

et al. 2002

IFIP Advances in Information and Communication Technology

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Abstract:High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution. By proving the effectiveness of universal test sequences produced by such a generation technique in detecting stuck-at, path delay and bridging faults, we demonstrate that using RSIC generation is one of the best and most practical way to reach a high level of defect coverage during BIST of digital circuits.

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Section: Introductionmentioning

confidence: 99%

Random Adjacent Sequences

David

Girard

Landrault

et al. 2002

IFIP Advances in Information and Communication Technology

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“…Two aspects play role here: the LFSR polynomial and seed and the test length. Several methods to compute the LFSR seed to achieve good fault coverage have been proposed [12,13]. However, for simplicity, we just repeatedly select the seed randomly, evaluate the fault coverage reached by using it, and select the best one.…”

Section: Pseudo-random Phasementioning

confidence: 99%

Column-matching based mixed-mode test pattern generator design technique for BIST

Fišer

Kubátová

2008

Microprocessors and Microsystems

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“…The general problem of circuit-specific customization of pseudo-random sequence generators has been vigorously studied for the last twenty years. Proposed solutions involve reseeding of LFSR [2,3,4,5,6,7,8,9,10], weighted random-pattern generation (WRPG) [11,12,13,14,15,16], and embedding of deterministic patterns in the pseudo-random sequence by using bitfixing or bit-flipping logic, sometimes in combination with Markov sources [17,18,19,20]. Along this spectrum of approaches, our contribution falls under WRPG because the 0, 1, and x values in a cube can be mapped to the very simple weight set, {0, 1, 0.5}.…”

Section: (Test Compaction Problem)mentioning

confidence: 99%