Efficient Test Compaction for Pseudo-Random Testing

Zhang, Sheng; Seth, Sharad; Bhattacharya, Bhaswar B.

doi:10.1109/ats.2005.55

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An efficient test-data compaction for low power VLSI testing

Chen

et al. 2008

2008 IEEE International Conference on Electro/Information Technology

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This paper presents an input test data compaction and scan power reduction technique. We present new design for testability (DFT) method to hold values when some of test data in test cubes are not need to be changed. In our implementation, we present new algorithm called 2-D compaction to compact test cubes as less as possible and fill unspecified bits with specified value when necessary. Experimental results show a high compaction ratio improvement and amount of test data bits is close to compression effect. It's suggested that our method is promising for greatly reduce peak power and heat dissipation. Index Terms------Testing, DFT, X filling, test data compaction237 978-1-4244-2030-8/08/$25.00 ©2008 IEEE.

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