On a Pin Versus Block Relationship For Partitions of Logic Graphs

Landman, B. S.; Russo, R.L.

doi:10.1109/t-c.1971.223159

Cited by 615 publications

(301 citation statements)

References 5 publications

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“…The need for a mix of segment lengths in island-style FPGA devices is motivated by the characteristics of benchmark designs targeted to the devices. The amount of interconnect required by a circuit has been found to be related to Rent's rule [123], a well-known relationship between the size of a group of logic and the number of its external connections. This relationship indicates that the amount of pins, P , needed for an amount of logic, G, grows as…”

Section: Detailed Island-style Routing Architecturementioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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Section: Detailed Island-style Routing Architecturementioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

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“…Rent's rule [12] predicts a slow but exponential increase in the complexity of the interconnect and this has been observed in the increased numbers of layers of metalisation.…”

Section: Toward Network-on-chipmentioning

confidence: 99%

Implications of Electronics Technology Trends for Algorithm Design

Greenfield¹,

Moore²

2009

The Computer Journal

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Scaling of electronics technology has brought us to a pivotal point in the design of computational devices. Technology scaling favours transistors over wires which has led us into an era where communication takes more time and consumes more power than the computation itself. This technology driver inevitably pushes us toward a communication-centric approach to algorithm design. To assess the efficiency of an algorithm we will need to be able to predict data movement both in time and space. We demonstrate that algorithms exhibit fractal like communication behaviour which is likely to help with such an analysis. Moreover, successfully exploiting these fractal properties will allow us to reduce communication, thereby increasing performance and power efficiency.

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“…Clearly concurrency (parallelism) would need to be exploited to convert this increase in device count to performance. Locality was required because the wire bandwidth at the periphery of a module was scaling only as the square root of the device count, much slower than the 2/3 power required by Rent^ rule [LanRus71]. Also, even in 1979 it was apparent that wires, not gates, limited the area, performance, and power of many modules.…”

Section: Twenty Years Of Vlsi Architecturementioning

confidence: 99%