VLSI Architecture: Past, Present, and Future

Dally, William J.; Lacy, Steve

doi:10.21236/ada419586

Cited by 5 publications

(3 citation statements)

References 10 publications

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“…7 presents simulation results for various superscalar processor designs. The number of critical path gates (Ncp) is extrapolated from [37] to represent pipeline delay from logic circuits. The family of solid-line curves represents local clock frequency for processors with different issue widths, while the dashed line represents cycle time for across-chip global wires.…”

Section: A a Superscalar Processor Designmentioning

confidence: 99%

Heterogeneous architecture models for interconnect-motivated system design

Chai

Taha

Wills

et al. 2000

IEEE Trans. VLSI Syst.

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On-chip interconnect demand is becoming the dominant factor in modern processor performance and must be estimated early in the design process. This paper presents a set of heterogeneous architectural models that combines architecture description and Rent's Rule-based wiring models. These architecture models allow flexible heterogeneous system specifications, enabling investigations of prospective designs in different technology scenarios. Comparisons against actual data demonstrate the models' effectiveness for architecture explorations with highly accurate estimations of local and global wiring demand, as well as chip area and cycle time. Simulation of two candidate system designs reveal trends in interconnect delay with increasing architectural complexity, and confirm the need for high computational locality and short global wires for future architectures.

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Section: A a Superscalar Processor Designmentioning

confidence: 99%

Heterogeneous architecture models for interconnect-motivated system design

Chai

Taha

Wills

et al. 2000

IEEE Trans. VLSI Syst.

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“…One of the main problems of single-chip multicore solutions, and probably the biggest one, is programmability since for several years manufacturers have retained the uniprocessor monolithic design approach to provide software compatibility [14]. Even if the multicore model suggests a great flexibility, the commercial multicore architectures (with more than 256 cores on the same chip) strongly relies on designtime resources mapping to deal with the huge hardware complexity [1,3], thus limiting flexibility and fault-tolerance, while leaving to the programmer the role to explicitly exploit parallelism.…”

Section: Introductionmentioning

confidence: 99%

Self-coordinated On-Chip Parallel Computing: A Swarm Intelligence Approach

Pani

Raffo

2010

Studies in Computational Intelligence

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Self organization is the property of some natural systems to organize themselves without a central coordination unit to perform specific tasks. Swarm Intelligence is a bioinspired paradigm coming from the observation of natural swarms, such as honey bees and bird flocks. Swarms exploit self organization to achieve coordination, speed-up and fault tolerance. This interesting paradigm has been applied in different research fields, mainly in robotics and optimization algorithms. Our pioneering studies about the application of this powerful paradigm to digital VLSI systems demonstrated that Swarm Intelligence can be applied to the design of scalable computing architectures composed of a large set of self-coordinated hardware agents. In this Chapter we present this approach with a review of our research works in this field from the first explorations to the latest results: the FPGA implementation of a coprocessing architecture expressly conceived resorting to the Swarm Intelligence principles. Some experimental results are presented to evaluate the main features of this innovative approach, which shows interesting performance improvements without any programming effort and without complex tools for compilation and mapping, compared to other state-of-the-art coprocessing architectures. F. Fernández de Vega, E. Cantú-Paz (Eds.): Paral. and Distrib. Comp. Intel., SCI 269, pp. 91-112.

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“…Essa rápida evolução deve continuar nos próximos anos. Atualmente, o desempenho das GPUs tem crescido numa taxa que excede a taxa de crescimento de desempenho observada nos microprocessadores de propósito geral: 225% ao ano para as GPUs [Fernando, 2004], contra um máximo de 50% do crescimento anual do desempenho das CPUs [Dally, 1999]. Contudo, tal evolução tem sido concentrada no melhoramento de técnicas de síntese de imagens em oposição ao melhoramento de técnicas de interação 3D.…”

Section: Evolução Do Hardware Gráficounclassified

Uma arquitetura de suporte a interações 3D integrada a GPU

Batagelo¹,

Wu²

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Tendo como hipótese de que o controle preciso do movimento de um cursor constitui uma das técnicas elementares para as tarefas de manipulação direta 3D, esta tese propõe uma arquitetura de suporte a controles configuráveis dos movimentos de cursores em relação a modelos deformados em hardware gráfico. De forma integrada ao fluxo programável de visualização, a arquitetura calcula atributos de geometria diferencial discreta dos modelos processados, codificando tais atributos em pixels de buffers de renderização não visíveis. Mostramos, através de estudos de casos, que o uso desses atributos é suficiente para estabelecer uma correspondência entre o espaço discreto do modelo renderizado na tela e o espaço contínuo do modelo submetido ao fluxo de visualização. Isto permite que os cursores sejam posicionados de forma consistente com aquilo que o usuário está visualizando, proporcionando uma interação mais acurada. Testes de desempenho e robustez são conduzidos para validar a arquitetura. Uma biblioteca de funções que encapsula a arquitetura é apresentada, juntamente com exemplos de tarefas de manipulação direta 3D implementadas através dela.

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VLSI Architecture: Past, Present, and Future

Abstract: This paper examines the impact of VLSI

Cited by 5 publications

References 10 publications

Heterogeneous architecture models for interconnect-motivated system design

Heterogeneous architecture models for interconnect-motivated system design

Self-coordinated On-Chip Parallel Computing: A Swarm Intelligence Approach

Uma arquitetura de suporte a interações 3D integrada a GPU

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