Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs

Bagheriye, Leila; Toofan, Siroos; Saeidi, Roghayeh; Moradi, Farshad

doi:10.1109/tvlsi.2018.2808140

Cited by 14 publications

(9 citation statements)

References 18 publications

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“…Offset-compensated high-speed sensing (OCHS) [ 31 ];…”

Section: Preliminarymentioning

confidence: 99%

“…Table 2 lists the qualitative comparison of different sensing circuits, including the number of sensing path, the number of reference, P-channel metal–oxide–semiconductor (pMOS) load type and the reference scheme (CM for current-mean, RM for resistance-mean). Only transistor counts and minimum TMR are reported in the comparison, as different CMOS and MTJ process were used to realize previous sensing circuits [ 27 , 28 , 29 , 30 , 31 , 32 ]. Further quantitative analysis will be performed in Section 3 .…”

Section: Preliminarymentioning

confidence: 99%

“…Conventionally, source degeneration and one-paired balanced reference scheme were used to improve process variation tolerance during MRAM sensing operation [ 27 ]. In [ 31 ], an offset-compensated high-speed sense amplifier (OCHS-SA) was implemented for high speed and high yield with offset voltage cancellation (see Figure 1 e). It generates a voltage difference between

and

path in pre-charge phase from

and

respectively.…”

Section: Preliminarymentioning

confidence: 99%

“…Table 2 summarizes and compares the recently published sensing circuits according their performance in [ 27 , 28 , 29 , 30 , 31 , 32 ]. In next sections, the above mentioned sensing circuits will be evaluated with 28-nm CMOS technology.…”

Section: Preliminarymentioning

confidence: 99%

“…( d ) Dynamic dual-reference (DDRS) SA [ 30 ]. ( e ) Offset-compensated high-speed (OCHS) SA [ 31 ]. ( f ) High-sensing margin, high speed and stability (HMSS)SA.…”

Section: Figurementioning

confidence: 99%

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

et al. 2021

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Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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“…Offset-compensated high-speed sensing (OCHS) [ 31 ];…”

Section: Preliminarymentioning

confidence: 99%

Section: Preliminarymentioning

confidence: 99%

and

path in pre-charge phase from

and

respectively.…”

Section: Preliminarymentioning

confidence: 99%

Section: Preliminarymentioning

confidence: 99%

“…( d ) Dynamic dual-reference (DDRS) SA [ 30 ]. ( e ) Offset-compensated high-speed (OCHS) SA [ 31 ]. ( f ) High-sensing margin, high speed and stability (HMSS)SA.…”

Section: Figurementioning

confidence: 99%

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

et al. 2021

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Reliability and Power Analysis of FinFET Based SRAM

Navaneetha¹,

Bikshalu

2021

Silicon

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Demand for accommodating more and new functionalities within a single chip such as SOC needs a novel devices and architecture such as FinFET device instead of MOSFET. FinFET is emerged as nonplanar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering, threshold voltage roll off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed.Reliability is one of key considerations in converting a proof of concept into reality. In this work Reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductor) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7nm bsimcmg PTM les in mentor graphics tool. The FinFET based SRAM shown low leakage, power dissipation, delay compared to existing conventional MOSFET based SRAM.

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Survey On the Sensing Techniques Used for Spin Transfer Torque MRAM

Kumari,

Yadav

2024

J. Inst. Eng. India Ser. B

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Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs

Cited by 14 publications

References 18 publications

Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Reliability and Power Analysis of FinFET Based SRAM

Survey On the Sensing Techniques Used for Spin Transfer Torque MRAM

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