Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Bian, Zhongjian; Xia, Hong; Guo, Yanan; Naviner, Lírida Alves de Barros; Ge, Wei; Cai, Hao

doi:10.3390/mi12050551

Cited by 5 publications

(2 citation statements)

References 42 publications

(77 reference statements)

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“…The choice of the comparator was mainly providing zero static power dissipation. In literature, MRAM-based sensing circuits have been well developed featuring low-power and high speed [36], [37]. Here, we have incorporated our in-house developed RRAM device [38] to demonstrates its advantage in the conventional Dynamic Latched Clocked Comparator (DLCC) by providing tunability.…”

Section: Rram-based Threshold Detectionmentioning

confidence: 99%

An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing

Maheshwari

Serb

Papavassiliou

et al. 2022

IEEE Trans. Circuits Syst. I

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In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with 'memimpedace' elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at 100 o C across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance's quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).

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Section: Rram-based Threshold Detectionmentioning

confidence: 99%

An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing

Maheshwari

Serb

Papavassiliou

et al. 2022

IEEE Trans. Circuits Syst. I

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“…The output of the circuits, which varies with the input sequence in the NMOS logic structure and the data present in the non-volatile logic, is sensed by the sense amplifier. The precharge sense amplifier (PCSA) [39], offset-compensated high-speed sensing (OCHS) [40], dynamic dual-reference sensing (DDRS) [41], latch offset cancellation sensing (LOC) [42], double switches and transmission gate access transistor sensing (DSTA) [43], and high-sensing margin, high-speed, and stability sensing (HMSS) [44] are amongst the current mode sensing circuits that have been investigated for STT-MRAMs. The data stored in the non-volatile logic are changed using the writing circuit.…”

Section: Logic-in-memory Architecturementioning

confidence: 99%

Polymorphic Hybrid CMOS-MTJ Logic Gates for Hardware Security Applications

et al. 2023

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Various hardware security concerns, such as hardware Trojans and IP piracy, have sparked studies in the security field employing alternatives to CMOS chips. Spintronic devices are among the most-promising alternatives to CMOS devices for applications that need low power consumption, non-volatility, and ease of integration with silicon substrates. This article looked at how hardware can be made more secure by utilizing the special features of spintronics devices. Spintronic-based devices can be used to build polymorphic gates (PGs), which conceal the functionality of the circuits during fabrication. Since spintronic devices such as magnetic tunnel junctions (MTJs) offer non-volatile properties, the state of these devices can be written only once after fabrication for correct functionality. Symmetric circuits using two-terminal MTJs and three-terminal MTJs were designed, analyzed, and compared in this article. The simulation results demonstrated how a single control signal can alter the functionality of the circuit, and the adversary would find it challenging to reverse-engineer the design due to the similarity of the logic blocks’ internal structures. The use of spintronic PGs in IC watermarking and fingerprinting was also explored in this article. The TSMC 65nm MOS technology was used in the Cadence Spectre simulator for all simulations in this work. For the comparison between the structures based on different MTJs, the physical dimension of the MTJs were kept precisely the same.

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