Off state incorporation into the 3 energy mode device lifetime modeling for advanced 40nm CMOS node

Bravaix, A.; Guérin, C.; Goguenheim, D.; Huard, V.; Roy, D.; Besset, C.; Renard, S.; Randriamihaja, Y. Mamy

doi:10.1109/irps.2010.5488852

Cited by 17 publications

(9 citation statements)

References 33 publications

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“…7 that the degradation of the C GD under off-state stress is due to an increase of the drain resistance without any degradation of the extrinsic capacitances. These impacts on the C GD coincide with that of the high energetic mode and confirm the continuity aspect introduced in [6]. Fig.…”

Section: Off-state Analysissupporting

confidence: 82%

“…The high energy of the minority carrier transport contributes to the degradation. Bravaix et al have already stated in [6] that off-state acts as a continuity of the high energetic HC mode.…”

Section: Off-state Analysismentioning

confidence: 97%

“…Then, the capacitance starts to show a strong bias dependence that can be attributed to the overlap capacitance degradation. Note that thanks to an adaptation of the BSIM model [5], one can also extract a local flat band voltage drift in the overlap region as done in [6]. In addition to the extrinsic capacitance, the drain parasitic resistance (R D ) is degraded.…”

Section: Low and High Energetic Hc Analysismentioning

confidence: 99%

See 2 more Smart Citations

An advanced RF-CV method as a powerful characterization tool for the description of HC induced defect generation at microscopic level

Negre

Roy

Scheer

et al. 2011

2011 IEEE International Integrated Reliability Workshop Final Report

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A MOS Capacitance-Voltage method in RadioFrequency domain is presented. Characterization at higher frequency is becoming essential especially for advanced technology nodes that are confronted with gate leakage. Contrary to all other present methods, a full exploitation of S-parameters is performed to get key information regarding defect localization. The technique allows for MOS parameter extraction of the intrinsic and extrinsic components which enhances the scope of the defect localization area. An application of this method is performed to physically analyse the impact of three different energetic hot carrier degradation modes and also point out the unique signature of each degradation mode.

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Section: Off-state Analysissupporting

confidence: 82%

Section: Off-state Analysismentioning

confidence: 97%

Section: Low and High Energetic Hc Analysismentioning

confidence: 99%

See 1 more Smart Citation

An advanced RF-CV method as a powerful characterization tool for the description of HC induced defect generation at microscopic level

Negre

Roy

Scheer

et al. 2011

2011 IEEE International Integrated Reliability Workshop Final Report

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“…In view of Non-Conducting HotCarrier [5] (NCHC), this high Vds can be allowed. But if the device is under condition of mixed stress with NCHC and regular HCI, it is not simple to estimate the device degradation.…”

Section: Application Examples and Discussionmentioning

confidence: 99%

Design-in reliability for over drive applications in advanced technology

Ahn

Yeh

Sowards³

et al. 2010

2010 IEEE International Integrated Reliability Workshop Final Report

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We present the FEOL reliability checking flow in advanced technology especially with over drive applications. We check gate bias values obtained from SPICE transient simulation against the maximum allowed value, Vg_max, to make sure robust gate dielectric reliability. We set up HSPICE MOSRA simulation procedure to let designers check the impact of BTI and HCI to each MOSFET device and the circuit performance at End-of-Lifetime (EOL). From HCI degradation analysis from HSPICE MOSRA, we obtained a good correlation between HCI damage and slew rate and conditions in which HCI degradation is negligible. We discuss on the selection of the stress conditions and monitor conditions to be checked. We applied HSPICE MOSRA to several over drive applications and were able to successfully justify them with careful modeling for HCI and NCHC in addition to BTI.

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“…The VD dependence of the time-axis scaling factor is also shown to be similar across different published reports. Fig.1 (a) shows the time-scaled IDSAT kinetics from different published sources: VD variation at fixed VG (VG<VD) and also at VG=VD, different T [31], VG and VD variations for off-and on-state modes [13], LCH and VD variations at VG=VD [12], and multiple LCH at DC and pulsed (VX~0.6*VD) conditions at fixed VD [4] for planar MOSFETs. FinFET results at multiple T under DC and pulsed (VX~0.8*VD) conditions but at fixed VD are also shown [1].…”

Section: Universality Of Hcdmentioning

confidence: 99%

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Sharma

Mahapatra

2020

IEEE J. Electron Devices Soc.

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A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain (VD) and gate (VG) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different methods such as shift in threshold voltage (VT), linear (IDLIN) and saturation (IDSAT) drain current and charge pumping current (ICP), for off and on-state stress. The model is validated using measured data from conventional, Lightly Doped Drain (LDD) and Drain Extended (DE) MOSFETs, FinFETs and Gate All Around Nano Sheet (GAA-NS) FETs. Parametric drift due to Bias Temperature Instability (BTI) stress in the presence of VD is included. Impact due to Self-Heating (SH) and BTI-HCD coupling are considered. SPICE compatibility is shown by cycleby-cycle simulation of various Ring Oscillator (RO) circuits.

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Off state incorporation into the 3 energy mode device lifetime modeling for advanced 40nm CMOS node

Cited by 17 publications

References 33 publications

An advanced RF-CV method as a powerful characterization tool for the description of HC induced defect generation at microscopic level

An advanced RF-CV method as a powerful characterization tool for the description of HC induced defect generation at microscopic level

Design-in reliability for over drive applications in advanced technology

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

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Off state incorporation into the 3 energy mode device lifetime modeling for advanced 40nm CMOS node

Cited by 17 publications

References 33 publications

An advanced RF-CV method as a powerful characterization tool for the description of HC induced defect generation at microscopic level

An advanced RF-CV method as a powerful characterization tool for the description of HC induced defect generation at microscopic level

Design-in reliability for over drive applications in advanced technology

Modeling of HCD Kinetics Under Full VG – VD Space, Different Experimental Conditions and Across Different Device Architectures

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Product

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Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures