An interface characterization technique, termed the Fermi-level efficiency (FLE) method, is proposed for evaluating the passivation level of high trap density oxide-semiconductor interfaces. Based on the characteristic charge trapping time-energy relation and the conductance method, the FLE method examines the Fermi-level displacement at the oxide-semiconductor interface under applied gate bias. The obtained Fermi-level efficiencies can be used to assess the interface qualities of metal-oxide-semiconductor devices with III-V and other novel substrate materials.
RF reliability is becoming an increasing concern for actual technology platforms. In this context, small signal equivalent circuit degradation under hot carrier stress is investigated. It is shown that some lumped elements such as the conductance, the transconductance, the gate-to-drain capacitance, and series resistances are degraded. The application of corrections based on physical phenomenon explains the major part of the hot carrier impact on the small signal equivalent circuit. Furthermore, the overlap gate-to-drain capacitance degradation is emphasized.
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