The Fermi-level efficiency method and its applications on high interface trap density oxide-semiconductor interfaces

Abstract

An interface characterization technique, termed the Fermi-level efficiency (FLE) method, is proposed for evaluating the passivation level of high trap density oxide-semiconductor interfaces. Based on the characteristic charge trapping time-energy relation and the conductance method, the FLE method examines the Fermi-level displacement at the oxide-semiconductor interface under applied gate bias. The obtained Fermi-level efficiencies can be used to assess the interface qualities of metal-oxide-semiconductor devices with III-V and other novel substrate materials.

Scaled ZrO2 dielectrics for In0.53Ga0.47As gate stacks with low interface trap densities

“…Such maps provide a measure of Fermi level efficiency. 19 Here, G p =Axq À Á max shifts more than two orders of magnitude in frequency as the gate bias is changed between À0.25 and À0.75 V, consistent with a large band bending in response to a change in gate bias. The G p =Axq À Á max values (see scale bar on the right) can be used to estimate the D it by multiplication with a factor of $2.5.…”

Influence of plasma-based in-situ surface cleaning procedures on HfO2/In0.53Ga0.47As gate stack properties

“…The maps also indicate how efficient the Fermi level moves around midgap as a function of gate bias. 19 For both samples, the peaks shift more than two orders of magnitude in frequency as the gate bias is changed between 0 and À1 V. For the recipe B sample, the narrower trace additionally suggests larger band bending in response to a change in gate bias.…”

Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution

“…A series of conductance peaks measured under different frequencies and gate biases at depletion describes the positions 97-4244-5640-6/09/$26.00 ©2009 IEEE IEDM09-327 13.3.1 and the continuous movement of the surface Fermi-level, named the Fermi-level trace, and reflects the electrical modulation of a MOS system. The movement of the surface Fermi-level and its efficiency [7] or steepness with respect to gate bias change give important insights to the interface trap density distribution D it (E) within the measurement window defined by the charge trapping characteristics. This Fermi-level trace and efficiency concepts help explain the conductance plots of Fig.…”