Octagonal MOSFET: Reliable device for low power analog applications

Joly, Y.; Lopez, L.; Portal, Jean‐Michel; Aziza, Hassen; Masson, Pascal Le; Ogier, Jean-Luc; Bert, Y.; Julien, Franck; Fornara, P.

doi:10.1109/essderc.2011.6044176

Cited by 5 publications

(2 citation statements)

References 10 publications

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“…In this context, alternatives to classical planar MOSFETs have emerged in the last few years such as multiple-gate transistors [2], triple gate transistors [3], octagonal transistors [4], vertical MOS transistors [5], gate all around transistors [6], and the most relevant double gate SOI MOSFETs [7][8][9] and FinFETs [10][11][12][13] architectures. Alternatively, and mostly for passive devices, deep silicon trenches are used in different ways to increase integration density (insulators, sensors, or capacitors [14]).…”

Section: Introductionmentioning

confidence: 99%

AC stress analysis of trench-based multi-gate transistors in a 40 nm e-NVM technology

Gay

Marca

Aziza

et al. 2022

Microelectronics Reliability

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Section: Introductionmentioning

confidence: 99%

AC stress analysis of trench-based multi-gate transistors in a 40 nm e-NVM technology

Gay

Marca

Aziza

et al. 2022

Microelectronics Reliability

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“…The capacitive coupling of interconnections is embedded in the layout structures of high voltage power MOSFETs. The previously investigated structures such as overlapping circulargate structure [7], octagonal structure [8], hexagonal structure [9], waffle-shaped structure [10], and hybrid waffle structure [11] are commonly not permitted by the polysilicon DRC (Design Rule Check) rules in deep submicron processes. The waffle-shaped structure with the angled non-symmetrical connections leads to current unbalance and is therefore not optimal for high current applications [10].…”

Section: Introductionmentioning

confidence: 99%

Layout capacitive coupling and structure impacts on integrated high voltage power MOSFETs

Fan

Knott

Jørgensen

2016

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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The switching performances of the integrated high voltage power MOSFETs that have prevailing interconnection matrices are being heavily influenced by the parasitic capacitive coupling of on-chip metal wires. The mechanism of the side-byside coupling is generally known, however, the layer-to-layer coupling and the comparison of the layout impacts have not been well established. This paper presents modeling of parasitic mutual coupling to analyze the parasitic capacitance directly coupled between two on-chip metal wires. The accurate 3D field solver analysis for the comparable dimensions shows that the layer-to-layer coupling can contribute higher impacts than the well-known side-by-side coupling. Four layout structures are then proposed and implemented in a 0.18 µm partial SOI process for 100 V integrated power MOSFETs with a die area 2.31 mm 2. The post-layout comparison using an industrial 2D extraction tool shows that the side-by-side coupling dominated structure can perform better than the layer-to-layer coupling dominated structure, in terms of on-resistance times input or output capacitance, by 9.2% and 4.9%, respectively.

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