OASIS-based data preparation flows: progress report on containing data size explosion

Schulze, Steffen; LaCour, Pat; Grodd, Laurence

doi:10.1117/12.535683

Cited by 5 publications

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References 3 publications

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“…Figure 3 illustrates the impact of hierarchy on the file size. An example data set sees 10x file size reduction if expressed with the hierarchical OASIS format compared to the commonly used MEBES format [7]. When the data set is converted into a VSB format the output size is significantly smaller when the input is hierarchically compared to a flat input data set that produces a larger output file.…”

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The prospects for hierarchical data processing with growing complexity of the post-tapeout flow

Schulze

Sahouria

2005

Design and Process Integration for Microelectronic Manufacturing III

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The drive of the semiconductor industry towards smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making. The wavelength gap in lithography and process effects as well as dependencies on the design content have led to the tremendous variety of resolution enhancement techniques and process correction approaches that are currently applied to a design on its path to manufacturing. As the 65nm nodes become production ready and the 45nm node shifts into the focus of the development effects like flare in wafer exposure, fogging effects in ebeam mask exposure and others that previously could be ignored are becoming significant so that their correction prior to manufacturing is required. That means additional correction steps are necessary to complete the data preparation. These put a larger burden on the data processing path and raise concerns over data volume and processing time limitations. Hierarchical processing methods have proven very effective in the past to keep data volumes and processing time in control. The paper explores the design trends and the potential of hierarchical processing under the new circumstances. Extended data flows with a variety of correction steps are investigated. Experimental results that demonstrate the benefit of hierarchical methods in conjunction with parallel processing methods like multithreading and distributed processing are provided. The benefit of introducing more effective data formats like OASIS in these flows will be illustrated.Historically the completion of a design was marked by the full chip verification and the delivery of a DRC an LVS clean layout. The transition of the data in form of GDSII into the mask writer format was usually a simple two step process -application of a general process bias (combination of mask and wafer lithography) and fracturing/formatting. The implementation of this simple flow was frequently shifted from the mask supplier side to the data supplier side since it was not very demanding [1]. A common flow as it is encountered today looks quite different. Figure 1 gives an example of a typical sequence as encountered in 90nm or 65nm data flows. The complexity is largely driven by the variety of processing effects that require data correction -CMP and etch processes drive the need for leveling pattern density via fill or slotting. These structures are printable elements and are inserted into the layout as part of the preprocessing prior to corrections for the imaging. A next step is rules based data corrections. This includes the insertion of non-printable assist-features for process window improvement for isolated features as well as other rules based corrections like a table driven OPC or target correction. Alternately, a phase shifting mask set can be derived to print the design pattern. After the contents of the layout are fully defined the model based OPC is applied. This functional block is followed by verification ste...

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confidence: 99%