Numerical Analysis of Slow Current Transients and Power Compression in GaAs FETs

Kazami, Y.; Kasai, D.; Horio, K.

doi:10.1109/ted.2004.837383

Cited by 25 publications

(19 citation statements)

References 18 publications

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“…It should be noted that the existence of surface states is shown to become a cause of gate lag [4,6] and the related current collapse [7] in GaAs MESFETs. The situation may be similar in GaN FETs.…”

Section: Resultsmentioning

confidence: 99%

“…We have next calculated a case when V D and V G are both changed abruptly [7]. Fig.6 shows the turn-on characteristics (E C -E DD is 1.0 eV) when V G is changed from the threshold voltage V th (-11.5 V) to 0 V. The off-state drain voltage V Doff is 20 V, and the parameter is the on-state drain voltage V Don .…”

Section: Current Collapsementioning

confidence: 99%

“…These are serious problems, and there are many experimental results reported on these phenomena. But few theoretical results have been reported for GaN-based FETs, although several numerical analyses were made for GaAs-based FETs [3][4][5][6][7]. Therefore, in this work, we have made transient simulation of a GaN MESFET in which deep levels in a semi-insulating buffer layer is considered, and discussed how the slow current transients and the current collapse could be reproduced.…”

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confidence: 99%

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Deep-level effects on slow current transients and current collapse in GaN MESFETs

Yonemoto

Horio

2004

13th International Conference on Semiconducting and Insulating Materials, 2004. SIMC-XIII-2004.

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Slow current transients in a GaN MESFET are analyzed by two-dimensional simulation in which deep levels in a semi-insulating buffer layer is considered.It is shown that when the drain voltage V D is raised abruptly, the drain current overshoots the steady-state value, and when V D is lowered, the drain current remains at a low value for some periods, showing drain lag behavior. This drain lag is shown to become a cause of so-called current collapse in the GaN MESFET. IntroductionRecently, GaN-based FETs have received great interest because of their potential applications to high power and high temperature microwave devices [1]. However, slow current transients are often observed even if the drain voltage or the gate voltage is changed abruptly [2]. This is called drain lag or gate lag, and is problematic in circuit applications. The slow transients mean that the DC I-V curves and the AC I-V curves become quite different, resulting in lower AC power available than that expected from the DC operation [1,2]. This is called power compression or current collapse in the GaN-device field. These are serious problems, and there are many experimental results reported on these phenomena. But few theoretical results have been reported for GaN-based FETs, although several numerical analyses were made for GaAs-based FETs [3][4][5][6][7]. Therefore, in this work, we have made transient simulation of a GaN MESFET in which deep levels in a semi-insulating buffer layer is considered, and discussed how the slow current transients and the current collapse could be reproduced. 2.Physical Model Fig.1 shows a device structure analyzed in this study. The donor density in the active layer is 2x10 17 cm -3 , and its thickness is 0.2 µm. This structure has a semi-insulating buffer layer, and is similar to a GaAs MESFET that has a semi-insulating substrate. As a model for the semi-insulating buffer layer, we use a three level compensation model which includes a shallow donor, a deep donor and a deep acceptor. Some experiments show that two levels (E C -1.75 eV, E C -2.85 eV) are associated with current collapse (or power compression) in GaN-based FETs with a semi-insulating buffer layer [2], so that we use energy levels of E C -2.85 eV (or E V + 0.6 eV) for the deep acceptor and of E C -1.75 eV for the deep donor, as shown in Fig.2. Other experiments show shallower energy levels for the deep donor [8,9], and hence we vary the deep donor's energy level (E DD ) as a parameter. Here, the deep donor's density (N DD ) and the deep acceptor's density (N DA ) are typically set to 5x10 16 cm -3 and 2x10 16 cm -3 , respectively.

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Section: Resultsmentioning

confidence: 99%

Section: Current Collapsementioning

confidence: 99%

mentioning

confidence: 99%

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Deep-level effects on slow current transients and current collapse in GaN MESFETs

Yonemoto

Horio

2004

13th International Conference on Semiconducting and Insulating Materials, 2004. SIMC-XIII-2004.

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“…These are serious problems, and there are many experimental works reported on these phenomena. But few theoretical works have been reported for GaN-based FETs [4,5], although several numerical analyses were made for GaAs-based FETs [6]. In Ref.…”

Section: Introductionmentioning

confidence: 99%

Simulation of slow current transients and current collapse in GaN FETs

et al. 2006

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Two-dimensional transient simulations of GaNMESFETs are performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. When the drain voltage V D is raised abruptly (while keeping the gate voltage V G constant), the drain current I D overshoots the steady-state value, and when V D is lowered abruptly, I D remains a low value for some periods, showing drain-lag behavior. These are explained by the deep donor's electron capturing and electron emission processes. We also calculate a case when both V D and V G are changed abruptly from an off point, and quasi-pulsed I-V curves are derived from the transient characteristics. It is shown that the drain currents in the pulsed I-V curves are rather lower than those in the steady state, indicating that so-called current collapse could occur due to deep levels in the semi-insulating buffer layer. It is also shown that the current collapse is more pronounced when V D is lowered from a higher voltage during turn-on, because the trapping effects become more significant.

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“…This is called power (current) compression [2,3]. These are serious problems, and there are many experimental works reported on these phenomena, but only a few theoretical works are reported for HFETs [4,5], although several numerical analyses were made for MESFETs [6][7][8][9][10]. Also, the lag phenomena were studied by changing only V D or V G .…”

Section: Introductionmentioning

confidence: 99%

Simulation of slow current transients and current compression in AlGaAs/GaAs HFETs

et al. 2006

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Two-dimensional transient simulations of AlGaAs/GaAs HFETs are performed in which substrate traps and surface states are considered. When the drain voltage is raised abruptly, the drain current overshoots the steady-state value, and when it is lowered abruptly, the drain current remains at a low value, showing drain-lag behavior. Turn-on characteristics are also calculated when both the gate voltage and the drain voltage are changed abruptly, and quasi-pulsed I -V curves are derived from them. It is shown that the drain lag due to substrate traps could become a cause of so-called current compression of the HFETs. It is also shown that gate lag due to surface states could become a major cause of the current compression.

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Numerical Analysis of Slow Current Transients and Power Compression in GaAs FETs

Cited by 25 publications

References 18 publications

Deep-level effects on slow current transients and current collapse in GaN MESFETs

Deep-level effects on slow current transients and current collapse in GaN MESFETs

Simulation of slow current transients and current collapse in GaN FETs

Simulation of slow current transients and current compression in AlGaAs/GaAs HFETs

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