NS-FDN: Near-Sensor Processing Architecture of Feature-Configurable Distributed Network for Beyond-Real-Time Always-on Keyword Spotting

Qin, Li; Liu, Changlu; Dong, Peiyan; Zhang, Yanming; Li, Tong; Lin, Sheng; Yang, Minda; Qiao, Fei; Wang, Yanzhi; Luo, Li; Yang, Huazhong

doi:10.1109/tcsi.2021.3059649

Cited by 24 publications

(4 citation statements)

References 23 publications

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“…Systematic integration of computing and sensor arrays has been widely studied to eliminate off-chip data transmission and reduce ADC bandwidth by combining CMOS image sensor and processors in one chip as known as PNS [2], [13], [21]- [24], or even integrating pixels and computation unit so-called PIS [12], [17], [25]- [28]. In [13], photocurrents are transformed into pulse-width modulation signals and a dedicated analog processor is designed to execute feature extraction reducing ADC power consumption.…”

Section: A Near-sensor and In-sensor Processingmentioning

confidence: 99%

PISA: A Binary-Weight Processing-In-Sensor Accelerator for Edge Image Processing

Angizi¹,

Tabrizchi²,

Roohi³

2022

Preprint

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This work proposes a Processing-In-Sensor Accelerator, namely PISA, as a flexible, energy-efficient, and highperformance solution for real-time and smart image processing in AI devices. PISA intrinsically implements a coarse-grained convolution operation in Binarized-Weight Neural Networks (BWNNs) leveraging a novel compute-pixel with non-volatile weight storage at the sensor side. This remarkably reduces the power consumption of data conversion and transmission to an off-chip processor. The design is completed with a bit-wise near-sensor processing-in-DRAM computing unit to process the remaining network layers. Once the object is detected, PISA switches to typical sensing mode to capture the image for a fine-grained convolution using only the near-sensor processing unit. Our circuit-to-application co-simulation results on a BWNN acceleration demonstrate acceptable accuracy on various image datasets in coarse-grained evaluation compared to baseline BWNN models, while PISA achieves a frame rate of 1000 and efficiency of ∼1.74 TOp/s/W. Lastly, PISA substantially reduces data conversion and transmission energy by ∼84% compared to a baseline CPU-sensor design.

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Section: A Near-sensor and In-sensor Processingmentioning

confidence: 99%

PISA: A Binary-Weight Processing-In-Sensor Accelerator for Edge Image Processing

Angizi¹,

Tabrizchi²,

Roohi³

2022

Preprint

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“…To improve data acquisition efficiency, a vast amount of research prototypes try to mimic human perception, creating a time-frequency representation of the microphone output, an approach known as silicon cochlea. [34]- [39]. Promising features in this approach are event-based processing and avoidance of traditional Nyquist sampling.…”

Section: B Kws Applications and Implementationsmentioning

confidence: 99%

Sub-mW Keyword Spotting on an MCU: Analog Binary Feature Extraction and Binary Neural Networks

Cerutti

Cavigelli²,

Andri³

et al. 2022

IEEE Trans. Circuits Syst. I

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Keyword spotting (KWS) is a crucial function enabling the interaction with the many ubiquitous smart devices in our surroundings, either activating them through wake-word or directly as a human-computer interface. For many applications, KWS is the entry point for our interactions with the device and, thus, an always-on workload. Many smart devices are mobile and their battery lifetime is heavily impacted by continuously running services. KWS and similar always-on services are thus the focus when optimizing the overall power consumption.This work addresses KWS energy-efficiency on low-cost microcontroller units (MCUs). We combine analog binary feature extraction with binary neural networks. By replacing the digital preprocessing with the proposed analog front-end, we show that the energy required for data acquisition and preprocessing can be reduced by 29×, cutting its share from a dominating 85% to a mere 16% of the overall energy consumption for our reference KWS application.Experimental evaluations on the Speech Commands Dataset show that the proposed system outperforms state-of-the-art accuracy and energy efficiency, respectively, by 1% and 4.3× on a 10-class dataset while providing a compelling accuracyenergy trade-off including a 2% accuracy drop for a 71× energy reduction.

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“…Systematic integration of computing and sensor arrays has been widely studied to eliminate off-chip data transmission and reduce ADC bandwidth by combining CMOS image sensors and processors in one chip, known as PNS [8][9][10][11][12], or even integrating pixels and computation unit so-called PIS [13][14][15][16]. In [9], photocurrents are transformed into pulse-width modulation signals, and a dedicated analog processor is designed to execute feature extraction reducing ADC power consumption.…”

Section: Near/in-sensor Processing Backgroundmentioning

confidence: 99%

Ocelli: Efficient Processing-in-Pixel Array Enabling Edge Inference of Ternary Neural Networks

Tabrizchi

Angizi

Roohi

2022

JLPEA

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Convolutional Neural Networks (CNNs), due to their recent successes, have gained lots of attention in various vision-based applications. They have proven to produce incredible results, especially on big data, that require high processing demands. However, CNN processing demands have limited their usage in embedded edge devices with constrained energy budgets and hardware. This paper proposes an efficient new architecture, namely Ocelli includes a ternary compute pixel (TCP) consisting of a CMOS-based pixel and a compute add-on. The proposed Ocelli architecture offers several features; (I) Because of the compute add-on, TCPs can produce ternary values (i.e., −1, 0, +1) regarding the light intensity as pixels’ inputs; (II) Ocelli realizes analog convolutions enabling low-precision ternary weight neural networks. Since the first layer’s convolution operations are the performance bottleneck of accelerators, Ocelli mitigates the overhead of analog buffers and analog-to-digital converters. Moreover, our design supports a zero-skipping scheme to further power reduction; (III) Ocelli exploits non-volatile magnetic RAMs to store CNN’s weights, which remarkably reduces the static power consumption; and finally, (IV) Ocelli has two modes, including sensing and processing. Once the object is detected, the architecture switches to the typical sensing mode to capture the image. Compared to the conventional pixels, it achieves an average 10% efficiency on its lane detection power consumption compared with existing edge detection algorithms. Moreover, considering different CNN workloads, our design shows more than 23% power efficiency over conventional designs, while it can achieve better accuracy.

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NS-FDN: Near-Sensor Processing Architecture of Feature-Configurable Distributed Network for Beyond-Real-Time Always-on Keyword Spotting

Cited by 24 publications

References 23 publications

PISA: A Binary-Weight Processing-In-Sensor Accelerator for Edge Image Processing

PISA: A Binary-Weight Processing-In-Sensor Accelerator for Edge Image Processing

Sub-mW Keyword Spotting on an MCU: Analog Binary Feature Extraction and Binary Neural Networks

Ocelli: Efficient Processing-in-Pixel Array Enabling Edge Inference of Ternary Neural Networks

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