Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications

Zhao, Qiang; Peng, Chunyu; Jun-ning, Chen; Lin, Zhiting; Wu, Xiulong

doi:10.1109/tvlsi.2019.2955865

Cited by 45 publications

(27 citation statements)

References 19 publications

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“…According to the published results RHPD-12T gives a better write performance than the proposed designs because it was designed for an improved write performance. We can also increase the write performance of the proposed SRAM design by adopting the technique from RHPD-12T [28]. Another proposed SRAM shows a better stability and read performance than RHPD-12.…”

Section: Wlwm(v)mentioning

confidence: 95%

“…This table shows the comparison of the effective cost in terms of the performance and stability of the SRAM chip with the other existing SRAM design. The proposed chip shows a better cost than existing designs in terms of most of the parameters [20,28]. Here, we compared the proposed design with the best suitable 12T and recently published 12T SRAM designs.…”

Section: Wlwm(v)mentioning

confidence: 99%

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Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements

Yadav

Kim

et al. 2021

Electronics

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The machine learning and convolutional neural network (CNN)-based intelligent artificial accelerator needs significant parallel data processing from the cache memory. The separate read port is mostly used to design built-in computational memory (CRAM) to reduce the data processing bottleneck. This memory uses multi-port reading and writing operations, which reduces stability and reliability. In this paper, we proposed a self-adaptive 12T SRAM cell to increase the read stability for multi-port operation. The self-adaptive technique increases stability and reliability. We increased the read stability by refreshing the storing node in the read mode of operation. The proposed technique also prevents the bit-interleaving problem. Further, we offered a butterfly-inspired SRAM bank to increase the performance and reduce the power dissipation. The proposed SRAM saves 12% more total power than the state-of-the-art 12T SRAM cell-based SRAM. We improve the write performance by 28.15% compared with the state-of-the-art 12T SRAM design. The total area overhead of the proposed architecture compared to the conventional 6T SRAM cell-based SRAM is only 1.9 times larger than the 6T SRAM cell.

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Section: Wlwm(v)mentioning

confidence: 95%

Section: Wlwm(v)mentioning

confidence: 99%

Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements

Yadav

Kim

et al. 2021

Electronics

View full text Add to dashboard Cite

show abstract

“…In addition, the recovery time after noise injection is relatively high, which makes it an unsuitable option for cache designs. RHPD12T [37] can recover from both SEUs and MEU. However, the design has high noise recovery time with a larger area and power overhead.…”

Section: ) Previous Cell Designs That Provide Seu Tolerance But Have ...mentioning

confidence: 97%

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

2022

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SRAM cells are widely used to design memory blocks of, e.g., caches, register files, and translation lookaside buffers. Depending on the SRAM application, the design requirements are different. For instance, in space applications, alongside energy efficiency, reliability is a main issue since the system is launched into space with a limited energy budget and stay exposed to high doses of radiation strikes for a long time. The Nwise cell has recently been proposed by the authors of this paper as the first highly reliable radiation hardened SRAM cell designed with 28nm FD-SOI. In this paper, inspired from the Nwise cell, we introduce another highly reliable radiation hardened SRAM cell, the Pwise cell, which is also designed with 28nm FD-SOI technology. Through comprehensive simulations of state-of-the-art cells, we show that both the Nwise and Pwise cells are competitive radiation hardened SRAMs to use in different memory blocks for space applications: (1) Both have the highest level of Single Event Upsets (SEU) tolerance capability for the temperature range deployed in space applications; further, both have the highest level of the tolerance capability to Multi Event Upsets (MEU). ( 2) Compared with the simulated cells that have comparable tolerance capability, the Nwise cell has low read delay and read power consumption, hence, it can be a good choice for space application cache designs, while the Pwise cell can be a proper candidate for space application register file designs since it has low write and read delay.

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“…A double exponential current source is used to inject current to a sensitive node for simulating the impact of a radiation strike. 11,16,29 A positive/negative transient pulse is generated at the drain diffusion region of a PMOS/NMOS transistor by altering the direction of the current source (Figure 7B/C). The expression of the injected double exponential current pulse to imitate an SEU is given by…”

Section: Soft-error Resilience and Critical Charge Comparisonmentioning

confidence: 99%

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Pal

Divya

et al. 2021

Circuit Theory & Apps

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In advanced technology, static random-access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high-energy particle strikes, which cause soft-error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation-hardened readdecoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read-decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02Â/1.06Â/1.07Â/1.08Â over NS10T/RHD12T/PS10T/RHBD10T at V DD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single-event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. K E Y W O R D Sdigital circuit, low power design, memory design, read stability, SRAM | INTRODUCTIONSatellites have become an integral part of human society, as we rely on satellite communication for a wide range of services, from meteorology to disaster monitoring, from navigation systems to military operations, and so on. 1 As the technology is advancing, lightweight satellites are replacing heavyweight satellites because of their higher manufacturing cost. 2 Since lightweight satellites have limited resources, they require high-density memory cells, and static random-access memory (SRAM) cells are the best alternative for space applications because of their high packing density and improved logic performance. 1 Space presents extreme conditions, like temperature fluctuations and radiation. Due to the weak geomagnetic field in space, radiation and energized particles increase. To withstand this harsh environment, special electronic components and circuits are used. Once a radiation particle strikes a logic circuit at its sensitive node, it generates electron-hole pairs (Figure 1A). These pairs become separated and accumulate at the sensitive node. 3 The accumulated charge at the sensitive node then generates a transient voltage pulse. If enough charge (i.e., critical charge, Q C ) is

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Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications

Cited by 45 publications

References 19 publications

Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements

Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

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