Novel Ultralow On-resistance Accumulation-mode LDMOS with Integrated Diodes

Wei, Jie; Ma, Zhen; Li, Congcong; Dai, Kaiwei; Luo, Xiaorong; Zhang, Bo

doi:10.1109/edtm50988.2021.9420939

Cited by 4 publications

(4 citation statements)

References 8 publications

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“…Obviously, the CFP-SID LDMOS obtains a better tradeoff relationship between the BV and R on,sp , and achieves a higher figure of merit (FOM = BV 2 /R on,sp ) of 11.42 MW cm −2 . Compared with the former RFP-SID LDMOS [25], the CFP-SID LDMOS decreases the R on,sp by 19.8% and improves the FOM value by 43.5%. The R on,sp of CFP-SID LDMOS is 53.8% lower than that of the Triple-RESURF LDMOS at the same BV.…”

Section: Resultsmentioning

confidence: 87%

“…However, the R on,sp of these methods is strongly dependent upon the N d , and charge imbalance will result in BV degradation. In the on-state, accumulation-mode current transportation is an efficient concept to achieve lower R on,sp and diminish its dependence on N d by forming high density electron accumulation layer [22][23][24][25]. For the previous accumulation LDMOS in [24,25], the electron accumulation layer in the on-state is discontinuous and the N-drift length (L D ) is not fully used to sustain the off-state BV.…”

Section: Introductionmentioning

confidence: 99%

“…In the on-state, accumulation-mode current transportation is an efficient concept to achieve lower R on,sp and diminish its dependence on N d by forming high density electron accumulation layer [22][23][24][25]. For the previous accumulation LDMOS in [24,25], the electron accumulation layer in the on-state is discontinuous and the N-drift length (L D ) is not fully used to sustain the off-state BV. In this work, a novel accumulation LDMOS with specific field plate layout and integrated diodes is proposed, to further decrease the R on,sp and improve the BV-R on,sp trade-off relationship.…”

Section: Introductionmentioning

confidence: 99%

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Simulation and experimental study on a high figure of merit LDMOS with ingenious layout design

Wei¹,

Dai²,

Ma³

et al. 2022

Semicond. Sci. Technol.

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To improve the tradeoff relationship between the specific on-resistance (Ron,sp) and breakdown voltage (BV), a novel lateral double-diffusion metal-oxide-semiconductor field effect transistor (LDMOSFET) with ingenious layout design is proposed and investigated by simulations and experiments. The proposed LDMOS features a specific convex-shape field plate (CFP) structure at source side and two separated integrated diodes (SID) at the drain side. On one hand, a continuous electron accumulation layer is formed from source to drain in the on-state, providing an ultralow current path to decrease the specific on-resistance (Ron,sp). On the other hand, the CFP and SID structures allow the proposed device to make full use of the drift length to sustain the off-state voltage, so that the novel device could maintain the same BV level with a shorten drift length. Thus, the proposed CFP-SID LDMOS achieves a much lower Ron,sp and better Ron,sp-BV tradeoff relationship. The experimental results illustrate that the CFP-SID LDMOS realizes a BV of 518V and Ron,sp of 23.5 mΩ·cm2 with a high figure of merit (FOM) of 11.42MW/cm2. Compared with the triple-RESURF LDMOS under the same BV, the proposed device decreases the Ron,sp by 53.8%.

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Section: Resultsmentioning

confidence: 87%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Simulation and experimental study on a high figure of merit LDMOS with ingenious layout design

Wei¹,

Dai²,

Ma³

et al. 2022

Semicond. Sci. Technol.

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show abstract

“…Based on our previous work of ALDMOS [11][12], this paper further analyses and illustrates a novel ALDMOS with two separated integrated diodes (SID) by simulations and experimental results. The measured results show that this novel SID ALDMOS decreases the Ron,sp by 33.7% compared with the triple RESURF LDMOS at the same BV.…”

Section: Introductionmentioning

confidence: 99%

Analyses and Experiments of Ultralow Specific On-Resistance LDMOS With Integrated Diodes

Wei

Dai

Luo

et al. 2021

IEEE J. Electron Devices Soc.

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An ultralow specific on-resistance (Ron,sp) accumulation-mode LDMOS (ALDMOS) is proposed and investigated by simulations and experiments. The proposed ALDMOS features two separated integrated diodes (SID) above the N-drift surface, which forms high density electron accumulation layer in the on-state. Meanwhile, the SID not only assists depleting the N-drift to increase the N-drift doping centration (Nd) in the off-state, but also modulates the lateral electric field to improve the breakdown voltage (BV). Thus, the proposed SID ALDMOS could achieve ultralow Ron,sp and maintain high BV simultaneously. The layout and key fabrication processes of the SID ALDMOS are demonstrated. The measured results show that the SID ALDMOS realizes a BV of 483V and Ron,sp of 29.3mΩcm 2 , with a high FOM value of 7.96MW/cm 2 . Its Ron,sp is decreased by 33.7% compared with triple RESURF LDMOS at the same BV.

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Investigating the Correlation Between Space Charge Modulation and ON-State Breakdown in Multiple RESURF DeMOS Devices

Mishra¹,

Gupta

2022

IEEE Access

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In this work, the ON-state performance of the drain-extended metal-oxide-semiconductor (DeMOS) device with multiple RESURF junctions in the drift region is explored. Although the additional RESURF implant offers a significant improvement in the breakdown voltage (VBD) and ON-resistance (RON) compared to the conventional DeMOS, it induces an early space charge modulation (SCM) initiated quasi-saturation (QS) effects and adversely impacts the ON-state breakdown of the device. Moreover, these devices are compared for a fixed breakdown voltage where a correlation between their analog/RF performance and QS effects is established. This work also presents and validates the design guideline for multiple RESURF devices that can alleviate the SCM/QS effects by 8% and improve the ON-state breakdown voltage by 35% compared to the standard device, thereby maximizing the ON-state performance of the device without compromising the OFF-state breakdown.INDEX TERMS Drain extended MOS (DeMOS), double RESURF, triple RESURF, space charge modulation (SCM), quasi-saturation (QS), ON-state breakdown.

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Novel Ultralow On-resistance Accumulation-mode LDMOS with Integrated Diodes

Cited by 4 publications

References 8 publications

Simulation and experimental study on a high figure of merit LDMOS with ingenious layout design

Simulation and experimental study on a high figure of merit LDMOS with ingenious layout design

Analyses and Experiments of Ultralow Specific On-Resistance LDMOS With Integrated Diodes

Investigating the Correlation Between Space Charge Modulation and ON-State Breakdown in Multiple RESURF DeMOS Devices

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