Analyses and Experiments of Ultralow Specific On-Resistance LDMOS With Integrated Diodes

Abstract

An ultralow specific on-resistance (Ron,sp) accumulation-mode LDMOS (ALDMOS) is proposed and investigated by simulations and experiments. The proposed ALDMOS features two separated integrated diodes (SID) above the N-drift surface, which forms high density electron accumulation layer in the on-state. Meanwhile, the SID not only assists depleting the N-drift to increase the N-drift doping centration (Nd) in the off-state, but also modulates the lateral electric field to improve the breakdown voltage (BV). Thus, the proposed SID ALDMOS could achieve ultralow Ron,sp and maintain high BV simultaneously. The layout and key fabrication processes of the SID ALDMOS are demonstrated. The measured results show that the SID ALDMOS realizes a BV of 483V and Ron,sp of 29.3mΩcm 2 , with a high FOM value of 7.96MW/cm 2 . Its Ron,sp is decreased by 33.7% compared with triple RESURF LDMOS at the same BV.

SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

“…With the rapid development of the power IC industry, LDMOS has been widely adopted due to its great compatibility with CMOS processes [2]. The tradeoff between the specific ON-resistance (R on,sp ) and breakdown voltage (BV) is a major issue to be considered in the design of SOI LDMOS [3], [4], [5], [6], [7]. In order to obtain the high breakdown characteristics and reduce the specific ON-resistance, high-k dielectric is employed in the SOI LDMOS.…”

500 V breakdown voltage in β‐Ga2O3 laterally diffused metal‐oxide‐semiconductor field‐effect transistor with 108 MW/cm2 power figure of merit

“…High-voltage ICs' operations can benefit from lateral doublediffused MOSFETs (LDMOSFET) on silicon-on-insulator (SOI) [1][2][3][4]. Also, the architecture of the buried oxide (BOX) must have received significant attention in the SOI high-voltage device to enhance the breakdown voltage (V BR ) since the SOI LDMOSFET suffers from small vertical V BR and is restricted from the active layer and BOX depths [5][6][7][8][9][10][11][12][13]. SOI devices provide exceptional benefits, such as minimal leakage current (I OFF ), incredibly rapid power switches, and significantly decreased parasitic capacitance for high-voltage ICs [14][15][16][17][18][19].…”

“…SOI devices provide exceptional benefits, such as minimal leakage current (I OFF ), incredibly rapid power switches, and significantly decreased parasitic capacitance for high-voltage ICs [14][15][16][17][18][19]. Over the last decade, a lot of research has examined LDMOS-FETs on SOI, and the characteristics and power figure of merit (PFOM) have been enhanced [8,9,[20][21][22][23]. Achieving high V BR is a major challenge in LDMOSFET, and many research works and different studies have been carried out in this field.…”

500 V Breakdown Voltage in β-Ga 2 O 3 LDMOSFET With 108 MW/cm 2 Power Figure of Merit

“…High-Voltage ICs operations can bene t from lateral double-diffused MOSFETs (LDMOSFET) on siliconon-insulator (SOI) [1][2][3][4]. Also, the architecture of the buried oxide (BOX) must have been received signi cant attention in the SOI high-voltage device to enhance the breakdown voltage (V BR ) since the SOI LDMOSFET suffers from small vertical V BR and restricted from the active layer and BOX depths [5][6][7][8][9]. SOI devices provide exceptional bene ts such as minimal leakage current (I OFF ), incredibly rapid power switches, and signi cantly decreased parasitic capacitance for high-voltage ICs [10][11][12][13][14][15].…”

“…SOI devices provide exceptional bene ts such as minimal leakage current (I OFF ), incredibly rapid power switches, and signi cantly decreased parasitic capacitance for high-voltage ICs [10][11][12][13][14][15]. Over the last decade, a lot of research has examined LDMOSFETs on SOI, and the characteristics and power gure of merit (PFOM) have been enhanced [8,9,[16][17][18][19]. Achieving high V BR is a major challenge in LDMOSFET research, and multiple studies have been investigated differently.…”