Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond

Ishibashi, M.; Horita, K.; Sawada, Mahito; Kitazawa, Masashi; Igarashi, M.; Kuroi, T.; Eimori, T.; Kobayashi, Kenzo; Inuishi, M.; Ohji, Yuzuru

doi:10.1143/jjap.44.2152

Cited by 12 publications

(6 citation statements)

References 3 publications

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“…21 Moreover, the gate direct tunneling current of holes in the inverted regime increase as STI-induced stress increases, as the growth of the gate oxide is slowed by the stress. 22 Therefore, uniaxial stress introduced by STI and silicide may need to be suppressed 23 to suppress junction leakage. 24 Other promising ways to induce uniaxial strain, such as use of a stress nitride contact etch-stop layer (CESL) 25,26 in the recessed source/drain regions filled with SiGe for pMOSs 27 and SiC for nMOSs, and the stress memorization technology 28,29 for nMOSs, are discussed below.…”

Section: Uniaxial Process-induced Strainmentioning

confidence: 99%

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Song

Zhou

et al. 2011

Journal of Elec Materi

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The aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal-oxide-semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/ drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new highmobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III-V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.

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Section: Uniaxial Process-induced Strainmentioning

confidence: 99%

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Song

Zhou

et al. 2011

Journal of Elec Materi

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“…TEM observations were performed using an HF-2210 transmission electron microscope (Hitachi High-Technologies). Moreover, convergent beam electron diffraction (CBED) [5][6][7][8] analysis was applied to analyze the mechanical strain at some local points of interest on cross-sectional TEM samples. CBED analysis was carried out on two samples with oxide recess amounts of 0 nm (measured value: 8 nm) and 50 nm (measured value: 60 nm).…”

Section: Contact Plugmentioning

confidence: 99%

Evaluation of the Strain around an Isolated Shallow Trench and the Impact of Stress on LSI Device Performance

Fukumoto

Kudo

Ota

et al. 2010

Jpn. J. Appl. Phys.

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We propose a stress-controlled fabrication process for shallow trench isolation (STI) that can reduce stress-originated leakage current. In this paper, the relationships between the electrical characteristics of a transistor and the STI fabrication process parameters were obtained by measurement. Direct measurements of mechanical strain around an STI structure were executed by convergent beam electron diffraction (CBED) analysis, and mechanical strain was simulated by the finite element method (FEM). Transmission electron microscopy (TEM) analysis was also performed. It was revealed that the undesirable leakage current in a transistor was caused by a dislocation in crystal silicon, which was induced by tensile strain perpendicular to the silicon surface. We also found that the mechanical strain is controllable by optimizing the amount of recess of the gap-fill oxide in the STI structure after chemical mechanical polishing (CMP).

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“…Nowadays, a technique for reliable stress evaluation at the micro-or nanoscale is in high demand for microdevices, such as semiconductor products and microelectromechanical systems (MEMS). In the semiconductor field, the control of stress or strain in a transistor channel (strained silicon), 1) and in a shallow trench isolation (STI) structure 2) has gained great significance for reducing the fluctuation of electrical mobility in the manufacturing process. To enhance the performance of a complementary metal oxide semiconductor, stress hybridization, i.e., a biaxial stress or combination of [110] and [100] single crystal silicon (SCS) structures on one chip, would be effective, [3][4][5] and presumably allows its stress or strain condition to be observed directly.…”

Section: Introductionmentioning

confidence: 99%

Micro-Raman spectroscopic analysis of single crystal silicon microstructures for surface stress mapping

Naka¹,

Kashiwagi²,

Nagai³

et al. 2015

Jpn. J. Appl. Phys.

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In this paper, an experimental analysis using a micro-Raman spectroscope for surface stress distribution in single crystal silicon (SCS) microstructures is described. Specially developed tensile test equipment applies a uniaxial tensile stress on SCS specimens with a 270 nm-high, 4 µm 2 convex structures in the gauge section. Raman spectra around the convex region are measured using an ultraviolet laser with an excitation line of 363.8 nm. The shape of the Raman spectrum on the flat surface is symmetrical, whereas that around the edge of the convex is asymmetrical due to the multi-stress condition. Two-curve fitting is adopted for the asymmetric spectrum obtained at the edge, and the stress distribution estimated by the two peak positions is much closer to finite element analysis (FEA) results than that obtained by the one peak position. In partial least squares (PLS) analysis that is performed at the edge of the convex section only, explanatory variables are Raman spectral parameters, such as peak position, peak intensity, and full width at half maximum, and the response variable is the FEA stress distribution. The plane stress distributions derived from PLS analyses on each component are in good agreement with that from FEA. The combination of micro-Raman spectroscopy and tensile testing enables us to directly determine the stress components as well as stress magnitudes on SCS microstructures.

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Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond

Cited by 12 publications

References 3 publications

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Evaluation of the Strain around an Isolated Shallow Trench and the Impact of Stress on LSI Device Performance

Micro-Raman spectroscopic analysis of single crystal silicon microstructures for surface stress mapping

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