Novel Quad interface MTJ technology and its first demonstration with high thermal stability and switching efficiency for STT-MRAM beyond 2Xnm

Nishioka, K.; Honjo, Haruo; Ikeda, Shoji; Watanabe, Takahito; Miura, Shigeto; Inoue, Hirofumi; Tanigawa, T.; Noguchi, Y.; Yasuhira, M.; Sato, Hideo; Endoh, Tetsuo

doi:10.23919/vlsit.2019.8776499

Cited by 27 publications

(12 citation statements)

References 1 publication

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“…Subsequently, several open-source PDKs are developed across 7nm to 180nm CMOS technologies, including Synopsys Generic Libraries 14nm, 28/32nm, 90nm [11], [24], Cadence University Program 45nm, 90nm, 180nm [12], ASAP PDK 7nm [13], and FreePDK 15nm [14], and 45nm [15]. There are improved versions of FreePDK with new add-on devices, such as RRAM [25] and MTJ [26]. We have summarized the different types of open-source PDKs in Table I…”

Section: B Open-source Pdks and Opportunitiesmentioning

confidence: 99%

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

Chen

Zhang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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With Moore's law reaching its limits, the use of new materials or new devices' structure has emerged as the next generation of CMOS devices. Among all, tunneling field-effect transistors (TFETs) have achieved a steep sub-threshold slope of less than 60mV/decade yet there is a lack of a complete process design kit (PDK) for large-scale circuit design. Hence, we present an open-source 15nm TFET PDK (15nmTFETPDK), which is based on FreePDK15 with additional support for open-source TFET models and its associated Cadence Virtuoso pcell in OA format and Mentor Calibre physical verification files. Our users can design their circuit in the Cadence Virtuoso platform and verify the consistency of the drawn layout and the circuit through the Calibre Platform. We hope that this open-source PDK allows them to further advance their research with new emerging devices.

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Section: B Open-source Pdks and Opportunitiesmentioning

confidence: 99%

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

Chen

Zhang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…In this manner, the power-gating technique is performed without losing internal data. Figure 3(a) shows the device structure of the magnetic tunnel junction (MTJ) device that comprises of two ferromagnetic layers separated by a tunnel barrier; the magnetization of the pinned layer (PL) is fixed, while that of the free layer (FL) is free to rotate [41][42][43]. The MTJ device is advantageous in that it is compatible with the CMOS process as it forms them in the back-end of the line.…”

Section: Nonvolatile Logicmentioning

confidence: 99%

Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic

Suzuki

Oka

Tamakoshi

et al. 2021

NOLTA

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Convolutional neural network (CNN) accelerators, particularly binarized CNN (BCNN) accelerators have proven to be effective for several artificial-intelligence-oriented several applications; however, their energy efficiency should be further improved for edge applications. In this paper, a design framework for an energy-efficient BCNN accelerator based on nonvolatile logic is presented. Designing BCNN accelerators using nonvolatile logic allows for the accelerators to exhibit a massively parallel and ultra-low standby power capability. Thus, a new design can be realized for accelerators that is different from that of conventional accelerators based solely on CMOS. Considering this, we discuss a concrete design considerations of nonvolatile BCNN accelerators. In fact, a systematic design flow of the nonvolatile BCNN is established by combining Vivado HLS and standard electronic design automation tools. As a typical design example, a BCNN accelerator for inferring 32 × 32 pixel MNIST dataset is designed using a 65-nm CMOS technology. By the logic-synthesis result, the proposed BCNN accelerator is estimated to consume 94.2% lower power than that of a conventional BCNN accelerator when the frame rate is 30 frames per second.

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“…An interesting idea to overcome this problem could be the recently presented Perpendicular Shape Anisotropy (PSA) MRAM in which the dimension (volume) of the free layer is drastically increased along the vertical axis while keeping a scaled radius [21]. Another promising option to enlarge ΔE is to increase the number of MgO-ferromagnetic interfaces [22].…”

Section: B Thermal Stability and Retention Time Of The Stored Informationmentioning

confidence: 99%

SEU Mechanisms in Spintronic Devices: Critical Parameters and Basic Effects

Coi

Adrianjohany²,

Pendina

et al. 2021

IEEE Trans. Nucl. Sci.

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The paper investigates radiation-induced switching mechanisms, temperature effects, breakdown voltage, sensitive volume and critical charge definitions for Spin-Transfer Torque Magnetic Tunnel Junction. Thermal spike model is adopted to estimate the temperature reached during heavy ion irradiation and temperature effects are suggested to be responsible for the magnetic properties degradation and for upset processes.

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Novel Quad interface MTJ technology and its first demonstration with high thermal stability and switching efficiency for STT-MRAM beyond 2Xnm

Cited by 27 publications

References 1 publication

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic

SEU Mechanisms in Spintronic Devices: Critical Parameters and Basic Effects

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