Abstract-Memories are currently a real bottleneck to design high speed and energy-efficient systems-on-chip. A significant increase of the performance gap between processors and memories is observed. On the other hand, an important proportion of total power is spent on memory systems due to the increasing trend of embedding volatile memory into systems-on-chip. For these reasons, STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) is seen as a promising alternative solution to traditional SRAM (Static Random Access Memory) thanks to its negligible leakage current, high density, and non-volatility. Nevertheless, the strategy of the same footprint replacement is constrained by the high write energy/latency of STT-MRAM. This paper performs a fine-grained evaluation of the cache organization to propose a hybrid cache memory architecture including both SRAM and STT-MRAM technologies.
Abstract-The scaling limits of CMOS have pushed many researchers to explore alternative technologies for beyond CMOS circuits. In addition to the increased device variability and process complexity led by the continuous decreasing size of CMOS transistors, heat dissipation effects limit the density and speed of current systems-on-chip. For beyond CMOS systems, the emerging memory technology STT-MRAM is seen as a promising alternative solution. This paper shows first how STT-MRAM can improve energy efficiency and reliability of future embedded systems. Then, a hybrid design exploration framework is presented to investigate the potential of STT-MRAM for high performance computing.
For embedded systems in harsh environments, a radiation robust circuit design is still an open challenge. As complementary metal oxide semiconductor (CMOS) processes get denser and smaller, their immunity towards particle strikes decreases drastically. Due to its radiation effects good tolerance and its inherent non-volatility, Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ) is considered a promising candidate for high reliability electronics. Nevertheless, when integrated in CMOS circuit, these magnetic devices could be still affected by upsets. To decrease the probability of this occurrence, a radiation robust setup is used to calibrate a physics-based 20 nm MTJ compact model, integrated in a 28 nm Fully Depleted Silicon on Insulator Technology. Thus, a radiation hardening by design (RHBD) solution is presented, where a non-volatile sequential block enables one to mitigate the Single Event Effects (SEEs).
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