Novel power MOSFET packaging technology doubles power density in synchronous buck converters for next generation microprocessors

Sawle, A.; Blake, C.; Marić, Dragana

doi:10.1109/apec.2002.989234

Cited by 21 publications

(6 citation statements)

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“…The higher current handling capability of the DirectFET TM populated VRM circuits is attributable to the combination of lower package parasitics and the increased thermal performance of the DirectFET TM package. The DirectFET TM package construction allows heat to be removed directly from the top of the package can assembly as well as through the can leads into the board [6,7]. This is referred to as 'dual sided cooling'.…”

Section: Effect Of Package Inductance On High Frequency Voltage Rementioning

confidence: 99%

High frequency DC:DC power conversion: the influence of package parasitics

Pavier

Sawle

Woodworth

et al.

Eighteenth Annual IEEE Applied Power Electronics Conference and Exposition, 2003. APEC '03.

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Operating power MOSFET devices at frequencies over 1MHz will pose significant challenges to established power electronic packages such as the D2-Pak and wirebonded SO-8 devices.In this paper the high frequency parasitic impedances of a range of power electronic packages are presented. Results show that a source mounted power package technology based upon a copper clip type assembly has considerably lower parasitic impedance compared to conventional power packaging at frequencies in the range of 500KHz to over 1MHz.The resistance of conventional packages recorded over this range of frequencies increases significantly as the frequency approaches 1Mhz. This is expected to be a result of skin effect related phenomena occurring in wire bonds and package leads. Package impedance data up to frequencies of 5MHz will be presented for a range of packages along with efficiency data recorded from devices operating in multi-phase buck converter circuits.

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Section: Effect Of Package Inductance On High Frequency Voltage Rementioning

confidence: 99%

High frequency DC:DC power conversion: the influence of package parasitics

Pavier

Sawle

Woodworth

et al.

Eighteenth Annual IEEE Applied Power Electronics Conference and Exposition, 2003. APEC '03.

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“…The curves suggest GaN as a potential candidate to replace Si and achieve breakthrough performance improvements of one order of magnitude in less than five years. These tremendous improvements may have to be accompanied by novel parasitic free packages that improve the existing LFPAK [143], DirectMOS [144] or PolarPak [145], as well as new driving solutions, as it shall be discussed in the following sections.…”

Section: Semiconductor Power Devicesmentioning

confidence: 99%

“…One effective measure to shorten the di/dt transition is by mitigating the source inductance of the power device. Packages like the DirectFET [144] and the PolarPAK® [145] are specially designed for that purpose, featuring a source inductance in the order of just 100pH. Although this and other solutions are well recognized under the assumption of ideal clamped inductive switching mode, their effectiveness becomes uncertain at high switching frequency due to the influence of neglected parasitic elements.…”

Section: Gate Driving Schemesmentioning

confidence: 99%

“…Innovation in power MOSFET packaging has followed a trend in SMT technologies to enable the reduction in footprint whilst maintaining levels of thermal resistance and reliability performance that compare to traditional larger packages. Solutions like the DirectFET [144] offer double sided cooling to achieve excellent heat removal capabilities around 1K/W with the size similar to SOIC packages. The elimination of wire bonding, molding and lead frames further allows significant reduction of parasitic elements.…”

Section: Packaging and Integrationmentioning

confidence: 99%

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Prospects of voltage regulators for next generation computer microprocessors

López Julià

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Synchronous buck converter based multiphase architectures are evaluated to determine whether or not the most widespread voltage regulator topology can meet the power delivery requirements of next generation computer microprocessors. According to the prognostications, the load current will rise to 200A along with the decrease of the supply voltage to 0.5V and staggering tight dynamic and static load line tolerances. In view of these demands, researchers face serious challenges to bring forth compliant solutions that can further offer acceptable conversion efficiencies and minimum mainboard area occupancy. Among the most prominent investigation fronts are those surveying fundamental technology improvements aiming at making power semiconductor devices more effective at high switching frequency. The latter is of critical importance as the increase of the switching frequency is fundamentally recognized as the way forward to enhance power density conversion. Provided that switching losses must be kept low to enable the miniaturization of the filter components, one primary goal is to cope with semiconductor and system integration technologies enabling fast dynamic operation of ultra-low ON resistance power switches. This justifies the main focus of this thesis work, centered around a comprehensive analysis of the MOSFET switching behavior in the synchronous buck converter. The MOSFETs dynamic operation, far from being well describable with the traditional clamped inductive hard-switching mode, is strongly influenced by a number of frequently ignored linear and nonlinear parasitic elements that must be taken into account in order to fully predict real switching waveforms, understand their dynamics, and most importantly, identify and quantify the related mechanisms leading to heat generation. This will be revealed from in-depth investigations of the switched converter under fast switching speeds and heavy load. Recognizing the key relevance of appropriate modeling tools that support this task, the second focal point of the thesis aims at developing a number of suitable models for the switching analysis of power MOSFETs. Combined with a series of design guidelines and optimization procedures, these models form the basis of a proposed methodological approach, where numerical computations replace the usually enormous experimental effort to elucidate the most effective pathways towards reducing power losses. This gives rise to the concept referred to as virtual design loop, which is successfully applied to the development of a new power MOSFET technology offering outstanding dynamic and static performance characteristics. From a system perspective, the limits of the power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities.

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“…The recent advancement in power semiconductor packaging makes use of solder joints, instead of bond wires, to fabricate the chip scale/size package (CSP) switches, such as IR's FlipFET [5] and DirectFET [6], Hitachi's LFPAK [7] and Fairchild's MOSFET BGA [8] and a Bottomless SO-8 package [9]. They can help to achieve a higher structural integration level with their smaller footprint and better electrical and thermal performance.…”

Section: Introductionmentioning

confidence: 99%

A chip-level process for power switching module integration and packaging

Liang

Wyk

Lee

Conference Record of the 2004 IEEE Industry Applications Conference, 2004. 39th IAS Annual Meeting.

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A process module, incorporating embedding of multiple power semiconductor chips in a flat ceramic frame and planar metallzation interconnect technologies, has been developed to fabricate active power chip scale packages (CSPs), multichip modules (MCMs), and integrated power electronics modules (IPEMs). This integrated chips technology features structure compactness and process integrity, compared to other multilevel packaging methods. Thus, power switching module, including controller and driver, sensor and filter, and power switches can be manufactured with a planar integration technology and packaged in 3-D form. An example IPEM, incorporating power factor correction (PFC) and DC/DC switching stages for a distributed power system (DPS) front-end converter application, has been fabricated and characterized. The electrical performance improvement, which includes reduction in parasitics and increase in efficiency, has been demonstrated. Furthermore, a highly functional integrated PFC switching module with embedded capacitor, current sensor and doubled side cooling has been fabricated in an integrated planar process scheme. The obtained experimental results are presented with prototypes.

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Novel power MOSFET packaging technology doubles power density in synchronous buck converters for next generation microprocessors

Cited by 21 publications

References 0 publications

High frequency DC:DC power conversion: the influence of package parasitics

High frequency DC:DC power conversion: the influence of package parasitics

Prospects of voltage regulators for next generation computer microprocessors

A chip-level process for power switching module integration and packaging

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