Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors

Wang, Yuke; Tang, Yiyan; Jiang, Yingtao; Chung, Jin-Gyun; Song, Sang Seob; Lim, Myoung-Seob

doi:10.1109/tsp.2007.892722

Cited by 35 publications

(10 citation statements)

References 10 publications

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“…The m-CORDIC and CSD-based optimal hybrid rotation scheme reduces the necessary chip area and improves the performance of the proposed design. The precision of the proposed R2FB pipelined FFT processor was evaluated by measuring the average relative percentage error value across 1024 points, as shown in Equation (13). The results obtained via the standard functions of Matlab were used as a baseline for comparison with the results on hardware.…”

Section: Resultsmentioning

confidence: 99%

“…Thus, design of an efficient FFT processor is of great significance in meeting the requirements of real-time applications in terms of speed, accuracy, low cost, and a smaller chip area. The FFT algorithm is mainly implemented on field-programmable gate arrays (FPGAs) [10][11][12], which offer advantages such as higher performance, less design time, and lower costs than digital signal processor-based systems (DSPs) [13][14][15]. Moreover, the increasing gate density of FPGAs in recent years has enabled designers to implement data-parallel signal processing algorithms by using massively parallel architectures that can meet high-speed processing requirements; this has resulted in implementations on FPGA that deliver outstanding performance in many applications.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

et al. 2018

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Abstract:The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process via shift registers. The proposed design uses an optimal hybrid rotation scheme by combining the modified coordinate rotation digital computer (m-CORDIC) algorithm and a binary encoding technique based on canonical signed digit (CSD) for replacing the complex multipliers in FFT. The m-CORDIC algorithm, with an adaptive iterative monitoring process, improves the convergence of computation, whereas the CSD algorithm optimizes the multiplication of constants using a simple shift-add method. Therefore, the proposed design does not require the large memory typically entailed by existing designs to carry out twiddle factor multiplication in large-point FFT implementations, thereby reducing its area on the chip. Moreover, the proposed pipelined FFT processor uses only distributed logic resources and does not require expensive dedicated functional blocks. Experimental results show that the proposed design outperforms existing state-of-the-art approaches in speed by about 49% and in resource utilization by around 51%, while delivering the same accuracy and utilizing less chip area.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

et al. 2018

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“…However, we can achieve improvement on energy efficiency by above two orders of magnitude (36.1 GFLOPS/W vs. 0.12 GFLOPS/W); this enhancement is attributed to the specialized structure for a batch of small-size FFTs and the organization of SRAM and DDR memory for large-size FFTs. For TI TMS320C64X DSP chips, the optimized radix-2 DIF FFT codes, developed by Y. Wang [5], are compared in Table I, and we can achieve a 53Â average performance improvement.…”

Section: Prototypementioning

confidence: 99%

Transpose-free variable-size FFT accelerator based on-chip SRAM

Guo

Tang

Lei

et al. 2014

IEICE Electron. Express

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This paper presents a transpose-free variable-size fast fourier transform (FFT) accelerator on a digital signal processing (DSP) chip. Several parallel schemes are utilized to calculate a batch of smallsize FFT algorithms to achieve high performance and throughput. For middle-and large-size of FFT, we propose a transpose-free CooleyTukey scheme that uses the random access feature of on-chip SRAM memory to avoid the DDR access of matrix with column-wise and improves the utilization of DDR bandwidth. Experimental results show that our FFT accelerator, implemented with 65 mn library and run at 500 MHz, can achieve the energy efficiency improvement by two orders of magnitude compared with Intel Xeon CPU and obtain above 50# performance improvement compared with TI TMS320C64X DSP chip.

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“…These latter are classically stored as a N-sized complex vector, requiring O(N log(N)) accesses. In [21], a novel memory reference reduction method is introduced by grouping butterflies using the same twiddle factors together; therefore decreasing the number of memory references due to twiddle factors in DSPs by 76 %. Another FFT scheme is presented in [22], reducing the memory access frequency and multiplication operations.…”

Section: Introductionmentioning

confidence: 99%

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Bahtat

Belkouch

Elleaume

et al. 2016

EURASIP J. Adv. Signal Process.

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The fast Fourier transform (FFT) is perhaps today's most ubiquitous algorithm used with digital data; hence, it is still being studied extensively. Besides the benefit of reducing the arithmetic count in the FFT algorithm, memory references and scheme's projection on processor's architecture are critical for a fast and efficient implementation. One of the main bottlenecks is in the long latency memory accesses to butterflies' legs and in the redundant references to twiddle factors. In this paper, we describe a new FFT implementation on high-end very long instruction word (VLIW) digital signal processors (DSP), which presents improved performance in terms of clock cycles due to the resulting low-level resource balance and to the reduced memory accesses of twiddle factors. The method introduces a tradeoff parameter between accuracy and speed. Additionally, we suggest a cache-efficient implementation methodology for the FFT, dependently on the provided VLIW hardware resources and cache structure. Experimental results on a TI VLIW DSP show that our method reduces the number of clock cycles by an average of 51 % (2 times acceleration) when compared to the most assembly-optimized and vendor-tuned FFT libraries. The FFT was generated using an instruction-level scheduling heuristic. It is a modulo-based register-sensitive scheduling algorithm, which is able to compute an aggressively efficient sequence of VLIW instructions for the FFT, maximizing the parallelism rate and minimizing clock cycles and register usage.

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Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors

Cited by 35 publications

References 10 publications

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

Transpose-free variable-size FFT accelerator based on-chip SRAM

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

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