Novel high-yield trilayer resist process for 0.1 μm T-gate fabrication

Watanabe

Phys. Status Solidi (c)

et al. 2008

We measured DC and RF characteristics at 300 and 16 K of sub‐100‐nm‐gate AlGaN/GaN metal‐insulator‐semiconductor (MIS) high electron mobility transistors (HEMTs) that had SiN/SiO2/SiN triple‐layer insulators. The drain‐source current and the maximum transconductance increased as expected. We observed an increase of 14 to 28% in the value of cutoff frequency fT at 16 K over that at 300 K. At 16 K, we obtained a maximum fT of 176 GHz at a gate length Lg of 45 nm. We estimated the average electron velocity under the gate by a transit time analysis. The average velocities were 2.2 × 107 cm/s at 300 K and 2.7 × 107 cm/s at 16 K. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

mentioning

confidence: 99%

Cryogenic characteristics of sub‐100‐nm‐gate AlGaN/GaN MIS‐HEMTs

Watanabe

Phys. Status Solidi (c)

et al. 2008

“…The fabrication process was as follows: We used SiN/SiO 2 /SiN triple-layer insulators. [10] on the topmost SiN film, a T-shaped gate pattern was directly formed by EB exposure. A 50-keV EB machine, JBX-6000 developed by JEOL, was used for EB lithography.…”

mentioning

confidence: 99%

Effect of temperature on cryogenic characteristics of AlGaN/GaN MIS‐HEMTs

Watanabe

Phys. Status Solidi (c)

et al. 2009

We measured the DC and RF characteristics at 300, 220, 150, 77, and 16 K of AlGaN/GaN metal‐insulator‐semiconductor (MIS) high electron mobility transistors (HEMTs) with SiN/SiO2/SiN triple‐layer insulators. The values of the cutoff frequency fT and the maximum transconductance gm_max increased with a decrease in temperature at relatively high temperatures, i.e. between 150 and 300 K. At temperatures below 100 K, the values of fT and gm_max increased slightly. We also carried out Monte Carlo simulations of electron transport in bulk GaN at various temperatures and electric fields. The steady‐state drift velocity of electrons showed a trend similar to those of the values of fT and gm_max. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

“…A SiO 2 /SiN double-layer film was used as a mask material. A T-shaped gate pattern was directly written by EB exposure after coating with a triple-layer EB resist consisting of ZEP/PMGI/ZEP [5]. A 50-keV EB machine developed by JEOL was used for EB lithography.…”

mentioning

confidence: 99%

Fabrication of sub‐50‐nm‐gate i‐AlGaN/GaN HEMTs on sapphire

Ikeda

et al. 2003

phys. stat. sol. (c)

We fabricated sub-50-nm-gate i-AlGaN/GaN high electron mobility transistors (HEMTs) on sapphire and measured their DC and RF characteristics at room temperature. The fabricated HEMTs exhibited true device operation and good pinch-off characteristics down to a gate length L g of 25 nm. For the HEMTs with a source-drain spacing L sd of 2 µm, we obtained the L g dependence of the cutoff frequency f T under a drain-source voltage V ds of 3 V. The peak f T was measured to be 102 GHz at L g = 35 nm. At L g = 25 nm, f T started to decrease due to the short-channel effect. The highest f T of 110 GHz was obtained by reducing L sd from 2 to 1.5 µm and by increasing V ds from 3 to 4 V. . However, obtaining the electron peak velocity requires a much higher electric field for GaN (~140 kV/cm) than for In 0.53 Ga 0.47 As (~4 kV/cm). Reducing gate length L g is a straightforward method of obtaining a very high electric field, similar to applying a high voltage. For AlGaN/GaN HEMTs, the shortest reported L g is 50 nm [3]. We previously developed a fabrication technique for sub-50-nm-gate HEMTs for the InAlAs/InGaAs material system using electron beam (EB) lithography [4].In the present work, we used this technique to fabricate sub-50-nm-gate i-AlGaN/GaN HEMTs on sapphire and successfully tested true device operation.