Novel flowable CVD process technology for sub-20nm interlayer dielectrics

Kim, Hong-Gun; Lee, Seungheon; Lee, Jun–Won; Bae, Byoung-Jae; Choi, YongSoon; Koh, Young‐Sang; Yi, Hayoung; Hong, Eunki; Kang, Man-Sug; Nam, Seok Woo; Kang, Ho–Kyu; Chung, Chilhee; Park, Jinhyung; Cho, Namjin; Lee, Seungmoo

doi:10.1109/iitc.2012.6251590

Cited by 7 publications

(8 citation statements)

References 2 publications

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“…The requirements of ALD precursors are high volatility, thermal stability, and reactivity with substrate and reactants. TSA is a highly volatile and highly reactive Cl-free molecule with Si–N bonds, but it readily reacts with NH/NH 2 groups to form a silazane oligomer structure . In order to achieve monolayer growth of silicon nitride film while maintaining reactivity and volatility, a series of novel trisilylamine-derivative compounds were designed as the ALD silicon precursors, as shown in Figure .…”

Section: Resultsmentioning

confidence: 99%

Plasma-Enhanced Atomic Layer Deposition of Silicon Nitride Using a Novel Silylamine Precursor

Park

Jang²,

Yusup

et al. 2016

ACS Appl. Mater. Interfaces

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We report the plasma-enhanced atomic layer deposition (PEALD) of silicon nitride thin film using a silylamine compound as the silicon precursor. A series of silylamine compounds were designed by replacing SiH3 groups in trisilylamine by dimethylaminomethylsilyl or trimethylsilyl groups to obtain sufficient thermal stability. The silylamine compounds were synthesized through redistribution, amino-substitution, lithiation, and silylation reactions. Among them, bis(dimethylaminomethylsilyl)trimethylsilyl amine (C9H29N3Si3, DTDN2-H2) was selected as the silicon precursor because of the lowest bond dissociation energy and sufficient vapor pressures. The energies for adsorption and reaction of DTDN2-H2 with the silicon nitride surface were also calculated by density functional theory. PEALD silicon nitride thin films were prepared using DTDN2-H2 and N2 plasma. The PEALD process window was between 250 and 400 °C with a growth rate of 0.36 Å/cycle. The best film quality was obtained at 400 °C with a RF power of 100 W. The PEALD film prepared showed good bottom and sidewall coverages of ∼80% and ∼73%, respectively, on a trench-patterned wafer with an aspect ratio of 5.5.

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Section: Resultsmentioning

confidence: 99%

Plasma-Enhanced Atomic Layer Deposition of Silicon Nitride Using a Novel Silylamine Precursor

Park

Jang²,

Yusup

et al. 2016

ACS Appl. Mater. Interfaces

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“…The process of via formation has been described extensively [51], [52]. Controlling via formation provides another venue for obfuscation.…”

Section: B Interconnect Specific Mechanismsmentioning

confidence: 99%

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

Vijayakumar

Patil

Holcomb

et al. 2017

IEEE Trans.Inform.Forensic Secur.

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The threat of hardware reverse engineering is a growing concern for a large number of applications. A main defense strategy against reverse engineering is hardware obfuscation. In this work we investigate physical obfuscation techniques, which perform alterations of circuit elements that are difficult or impossible for an adversary to observe. Examples of such stealthy manipulations are changes in the doping concentrations or dielectric manipulations. An attacker will, thus, extract a netlist which does not correspond to the logic function of the device-under-attack. This approach of camouflaging has garnered recent attention in the literature.In this paper, we expound on this promising direction to conduct a systematic end-to-end study of the VLSI design process to find multiple ways to obfuscate a circuit for hardware security. This paper makes three major contributions. First, we provide a categorization of the available physical obfuscation techniques as it pertains to various design stages. There is a large and multidimensional design space for introducing obfuscated elements and mechanisms, and the proposed taxonomy is helpful for a systematic treatment. Second, we provide a review of the methods that have been proposed or in use. Third, we present recent and new device and logic-level techniques for design obfuscation. For each technique considered, we discuss feasibility of the approach and assess likelihood of its detection. Then we turn our focus to open research questions, and conclude with suggestions for future research directions.

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“…The flowable CVD process is a silazane based process used as a gap-fill material for shallow trench isolation (STI) or premetal dielectric (PMD) applications [3,4] the process is achieved by maintaining a liquid phase of the molecules during deposition thus, enabling a bottom-up gapfill by virtue of the surface tension in the film. The deposition is performed by a remote plasma system and the film is converted to stable silica phase by a post deposition cure process.…”

Section: A Flowable Cvd Depositionmentioning

confidence: 99%

Process monitoring using advanced inspection methodologies - a study with CVD

Gaan

Sun

et al. 2014

25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014)

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Defect free film deposition is one of the most challenging steps in CMOS manufacturing for 28nm process node and beyond. For precise control over surface, excellent uniformity and accurate material characteristics are required. IC manufacturers find it critical to monitor the film deposition process in terms of layer uniformity and other signatures/defects induced on the surface during the deposition process. In this work, an oxide layer deposited using flowable chemical vapor deposition (FCVD) process on a 300mm bare silicon wafer has been studied. Different process conditions with varying amount of precursor and reactant gases have been employed for the deposition of the oxide. The so called "haze" signatures and statistics found during inspection on the post-deposition surfaces are used to measure variation in surface quality, serving as a means to qualify the FCVD process.For this study, an FCVD tool fitted with two chambers with two sides each has been employed for the deposition of oxide. The integrated SURFmonitor feature of KLA-Tencor's SP3 -a blanket wafer defect inspection tool set -was successfully utilized to highlight the variation of the CVD tool's performance. Firstly, the overall study clearly demonstrates the capability of SURFmonitor to differentiate the process conditions between Process -1 and Process -2. Also, for a given process, it showcases the capability of differentiating between different deposition chambers. In addition, for a given process and specific chamber, grid analysis feature of SURFmonitor has been applied to highlight the within-spec and the out-of-spec areas for each of the wafers. The methodology described in this paper has already proven to be quite effective in monitoring the CVD process.

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Novel flowable CVD process technology for sub-20nm interlayer dielectrics

Cited by 7 publications

References 2 publications

Plasma-Enhanced Atomic Layer Deposition of Silicon Nitride Using a Novel Silylamine Precursor

Plasma-Enhanced Atomic Layer Deposition of Silicon Nitride Using a Novel Silylamine Precursor

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

Process monitoring using advanced inspection methodologies - a study with CVD

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