Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

Abstract

The threat of hardware reverse engineering is a growing concern for a large number of applications. A main defense strategy against reverse engineering is hardware obfuscation. In this work we investigate physical obfuscation techniques, which perform alterations of circuit elements that are difficult or impossible for an adversary to observe. Examples of such stealthy manipulations are changes in the doping concentrations or dielectric manipulations. An attacker will, thus, extract a netlist which does not correspond to the logic function of the device-under-attack. This approach of camouflaging has garnered recent attention in the literature.In this paper, we expound on this promising direction to conduct a systematic end-to-end study of the VLSI design process to find multiple ways to obfuscate a circuit for hardware security. This paper makes three major contributions. First, we provide a categorization of the available physical obfuscation techniques as it pertains to various design stages. There is a large and multidimensional design space for introducing obfuscated elements and mechanisms, and the proposed taxonomy is helpful for a systematic treatment. Second, we provide a review of the methods that have been proposed or in use. Third, we present recent and new device and logic-level techniques for design obfuscation. For each technique considered, we discuss feasibility of the approach and assess likelihood of its detection. Then we turn our focus to open research questions, and conclude with suggestions for future research directions.

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

“…II. Besides, a comprehensive overview of camouflaging is given in [24], and IP protection in general is reviewed in [25], [26].…”

Defense-in-depth: A recipe for logic locking to prevail

“…1) Device-level Hardware Obfuscation: At the device level, the layout of the device is disguised by introducing stuck-at-fault or delay manipulation [24]. Changes in doping concentration, manipulating inter-layer dielectric, inserting dummy logic and interconnects are conventional techniques to achieve a device-level obfuscated hardware.…”

Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

“…Hardware‐oriented security offers new Compementary metal‐oxide semiconductor (CMOS)‐based security primitives like true random number generators (TRNGs), physically unclonable functions, and other circuit design methodologies to make systems robust against security attacks . However, CMOS‐based security primitives consume high power and area and require additional source/drain doping variations to create stealthy manipulations for obfuscation . To overcome the limitations of CMOS, emerging devices are investigated by leveraging their inherent unique characteristics for hardware security .…”

“…[22][23][24] However, CMOS-based security primitives consume high power and area and require additional source/drain doping variations to create stealthy manipulations for obfuscation. [25][26][27] To overcome the limitations of CMOS, emerging devices are investigated by leveraging their inherent unique characteristics for hardware security. [28][29][30] The significance of TFET devices grabbed the attention of designers to explore the device properties exclusively for hardware security applications.…”