Novel, Effective and Cost-Efficient Method of Introducing Fluorine into Metal/Hf-based Gate Stack in MuGFET and Planar SOI Devices with Significant BTI Improvement

Shickova, A.; Collaer, N.; Zimmerman, Paul; Demand, M.; Simoen, Eddy; Pourtois, Geoffrey; DeKeersgieter, A.; Trojman, Lionel; Ferain, I.; Leys, Frederik; Boullart, Werner; Franquet, Alexis; Kaczer, B.; Jurczak, M.; Maes, H.E.; Groeseneken, G.

doi:10.1109/vlsit.2007.4339748

Cited by 15 publications

(6 citation statements)

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“…Such a behavior has been reported before for n-channel SOI MuGFETs [11], whereby the LF noise level increased for shorter channel devices, which was ascribed to damage at the edges of the (100) top surface gate oxide by spacer etching. These defects could be partly passivated by introducing F atoms during the etching [12]. At the same time, the second Lorentzian peak is not very dependent on the gate bias, suggesting that the GR centers are in the Si depletion region rather than in the oxide.…”

Section: Discussionmentioning

confidence: 99%

Low-frequency noise in triple-gate n-channel bulk FinFETs

Simoen

Aoulaiche

Collaert

et al. 2011

2011 21st International Conference on Noise and Fluctuations

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The noise in n-channel bulk MuGFETs with 2.5 nm SiON gate dielectric is reported. It is shown that besides number fluctuations-related 1/f noise often Generation-Recombination (GR) noise is observed. From a detailed study of the fin length and width dependence it is concluded that the GR noise preferentially occurs for short and wide transistors. The latter observation points to traps in the gate oxide edges as a possible source of the excess noise.

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Section: Discussionmentioning

confidence: 99%

Low-frequency noise in triple-gate n-channel bulk FinFETs

Simoen

Aoulaiche

Collaert

et al. 2011

2011 21st International Conference on Noise and Fluctuations

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“…Also post-fin etch H 2 annealing turned out to be helpful in improving NBTI. Moreover, it has recently been shown that the introduction of fluorine into metal/Hf-based gates stacks of both planar and multi-gate SOI devices improves both N-and PBTI [48], which points out that stable passivation of interface defects is key in this matter. On the other hand, mixed results have been obtained when introducing of high-κ cap layers: in the case of Dy 2 O 3 /SiO 2 little impact was reported [19], while abnormal BTI behavior has been seen for HfSiO/Dy 2 O 3 /TiN stacks [31].…”

Section: Reliabilitymentioning

confidence: 99%

Reliability performance characterization of SOI FinFETs

Claeys

Put

Rafı́

et al. 2009

2009 2nd International Workshop on Electron Devices and Semiconductor Technology

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FinFET devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling CMOS to 22 nm and below. Some physical characterization and reliability aspects of these devices are reviewed. Attention is given to transient floating body effects and low frequency noise, which may yield information on the materials' characteristics like carrier recombination lifetime or interface and oxide trap density. These methods can be useful to study the performance of these components under harsh operation conditions of low or high temperature, or at high bias voltages.

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“…It is believed that dry etching damage at the edges of the gate dielectric stack causes this enhanced 1/f noise and mobility degradation in short channel nMuGFETs. Recently, it has been suggested that using an SF 6 -based metal gate etch may improve the gate stack quality and drive current, without compromising the 1/f noise performance (50). The etch introduces F in the dielectric leading to an improved bias-temperature instability (BTI).…”

Section: Low Frequency Noise In Finfetsmentioning

confidence: 99%

Physical Characterization and Reliability Aspects of MuGFETs

Claeys

Simoen²,

Rafi

et al. 2007

ECS Trans.

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Multi-gate devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling to the 32 nm and below technology nodes. Worldwide much attention is given to FinFET and MuGFET device architectures. This paper reviews some physical characterization and reliability aspects of such devices. Attention is given to aspects such as transient floating body effects, their performance at both high and low temperatures, gate coupling effects and their low frequency noise behavior. In addition, their potential radiation hardness in view of space applications is outlined.

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Novel, Effective and Cost-Efficient Method of Introducing Fluorine into Metal/Hf-based Gate Stack in MuGFET and Planar SOI Devices with Significant BTI Improvement

Cited by 15 publications

References 1 publication

Low-frequency noise in triple-gate n-channel bulk FinFETs

Low-frequency noise in triple-gate n-channel bulk FinFETs

Reliability performance characterization of SOI FinFETs

Physical Characterization and Reliability Aspects of MuGFETs

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