Novel Deep Trench Buried-Body-Contact (DBBC) of 4F&lt;sup&gt;2&lt;/sup&gt; cell for sub 30nm DRAM technology

Cho, Youngseung; Hwang, Young‐Ha; Kim, Huijung; Lee, Eun-Ok; Hong, Soojin; Chung, Hyun-Woo; Kim, Daeik; Kim, Jiyoung; Oh, Youngtek; Hong, Hyeongsun; Jin, Gyoyoung; Chung, Chee Won

doi:10.1109/essderc.2012.6343366

Cited by 3 publications

(2 citation statements)

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“…Since it is necessary to use the epitaxial growth process of single-crystal silicon and realize the growth of inverted U-shaped oxide, the positions of the source and drain need to be interchanged. Therefore, the buried bit-line process is necessary [ 9 ]. The operating principle of the memory storage cells is the floating body effect.…”

Section: Proposed Structurementioning

confidence: 99%

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer

et al. 2022

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A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to not only have the characteristics of fast access, random read and integration of 4F2 cell, but also to realize good retention and deep scaling. At the same time, the new structure has the potential of scaling compared with the conventional capacitorless 1T DRAM.

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Section: Proposed Structurementioning

confidence: 99%

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer

et al. 2022

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“…As a result, it led the device architecture to move on non-planar and 3D structures. There are several device structures proposed and realized in 3D such as FinFET, 3D NAND, 4F 2 DRAM with 3D vertical gate and future device structures [1][2][3][4][5][6]. Device structures in 3D seem to allow further scaling down and boosted performances, but it also forced the fabrication processes to be adapted.…”

Section: Introductionmentioning

confidence: 99%

Conformal and Ultra Shallow Junction Formation Achieved Using a Pulsed-Laser Annealing Process Integrated With a Modified Plasma Assisted Doping Method

et al. 2020

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Recently, a shallow and conformal doping profile is required for promising 3D structured devices. In this study, we deposited the dopant phosphorus (P) using modified plasma assisted doping (PaD) followed by an annealing process to electrically activate the dopants. A rapid thermal annealing process (RTP) was the first approach tested for activation but it resulted in a deep junction (> 35 nm). To reduce the junction depth, we tried the flash lamp annealing process (FLP) to shorten the annealing time. We also predicted the annealing temperature by numerical thermal analysis, which reached 1,020 ℃. However, the FLP resulted in a deep junction (~ 30 nm), which was not shallow enough to suppress SCEs. Since an even shorter annealing process was required to form a USJ, we tried the laser annealing process (LAP) as a promising alternative. The LAP, which had a power density of 0.3 J/cm 2 , increased the surface temperature up to 1,100 ℃ with a shallow isothermal layer. Using the LAP, we achieved a USJ with an activated surface dopant concentration of 3.86×10 19 cm-3 and a junction depth of 10 nm, which will allow further scaling-down of devices.

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Array-Level Analysis of Magneto-Electric Random-Access Memory for High-Performance Embedded Applications

Lee

Ebrahimi

et al. 2017

IEEE Magn. Lett.

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Novel Deep Trench Buried-Body-Contact (DBBC) of 4F<sup>2</sup> cell for sub 30nm DRAM technology

Cited by 3 publications

References 2 publications

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer

Conformal and Ultra Shallow Junction Formation Achieved Using a Pulsed-Laser Annealing Process Integrated With a Modified Plasma Assisted Doping Method

Array-Level Analysis of Magneto-Electric Random-Access Memory for High-Performance Embedded Applications

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