Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

Ernst, T.; Dupré, C.; Isheden, Christian; Bernard, E.; Ritzenthaler, R.; Maffini-Alvaro, V.; Barbé, J. C.; Crecy, F. de; Toffoli, A.; Vizioz, C.; Borel, S.; Andrieu, F.; Delaye, V.; Lafond, D.; Rabille, G.; Hartmann, J.-M.; Rivoire, M.; Guillaumot, B.; Suhm, A.; Rivallin, P.; Faynot, O.; Ghibaudo, G.; Deleonibus, S.

doi:10.1109/iedm.2006.346955

Cited by 58 publications

(44 citation statements)

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“…In this respect, one-dimensional channel transistors, such as Si nanowire or Carbon nanotube FETs are among the most promising devices, due to increased performance [4] and for new functionalities [5]. Nevertheless, radically new technologies such as memristive devices also emerge towards the end of Moore's Law scaling, bringing completely new computational paradigms into the realm of design.…”

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confidence: 99%

Alternative design methodologies for the next generation logic switch

Sacchetto

Marchi

Micheli

et al. 2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Next generation logic switch devices are expected to rely on radically new technologies mainly due to the increasing difficulties and limitations of state-of-the-art CMOS switches, which, in turn, will also require innovative design methodologies that are distinctly different from those used for CMOS technologies. In this paper, three alternative emerging technologies are showcased in terms of their requirements for design implementation and in terms of potential advantages. First, a CMOS evolutionary approach based on vertically-stacked gate-all-around Si nanowire FETs is discussed. Next, an alternative design methodology based on ambipolar carbon nanotube FETs is presented. Finally, a novel approach based on the recently discovered memristive devices is presented, offering the possibility of combining memory and logic functions.

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confidence: 99%

Alternative design methodologies for the next generation logic switch

Sacchetto

Marchi

Micheli

et al. 2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Several groups, including the authors, have reported on variations of the TMAP-DRIE process for the fabrication of vertically stacked SiNWs arrays for micro-electro-mechanical-systems MEMS [12] and FET devices [13,14]. Nevertheless, the SiNW fabrication typically relies on thermal oxidation and/or hydrogen annealing techniques [7,8,13,14] which increase the temperature budget.…”

Section: Introductionmentioning

confidence: 99%

“…However, the throughput of the method is limited by the number of steps and the use of different substrates for nanowire growth and pattern transfer. Another method to produce vertically-stacked SiNWs is based on Si/SiGe epitaxy and has been reported by several groups [7][8][9]. The epitaxial method allows for very tight control of the film thickness and therefore, of nanowire dimensions; however, it lacks fabrication compatibility with conventional CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

Zervas

Sacchetto

Micheli

et al. 2011

Microelectronic Engineering

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“…MCFETs combine the advantages of excellent control of shortchannel effects with a high on-state current due to a multiple-gate architecture and the 3-D integration of vertically stacked channels. GAA devices with ultra-thin and narrow channels (about 10 nm) are seen as the ideal architecture for off-state current control of sub-10 nm gate lengths (Ernst et al, 2006). Meanwhile, the current density per surface of such a device is limited by the lithography pitch, which dictates the distance between nanowires.…”

Section: Introductionmentioning

confidence: 99%

“…As a result, intrinsic channels can be used leading to higher mobilities and drain currents. 3D Multi-Channel MOSFETs (MCFETs) have been recently proposed to achieve a higher current drivability and a significant enhancement of the on-state current over the off-state current ratio (I ON /I OFF ) (Bernard et al, 2007;Ernst et al, 2006) compared to conventional single channel devices. MCFETs combine the advantages of excellent control of shortchannel effects with a high on-state current due to a multiple-gate architecture and the 3-D integration of vertically stacked channels.…”

Section: Introductionmentioning

confidence: 99%