Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

Zervas, Michael; Sacchetto, Davide; Micheli, Giovanni De; Leblebici, Yusuf

doi:10.1016/j.mee.2011.06.013

Cited by 14 publications

(15 citation statements)

References 20 publications

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“…The devices are fabricated in a top-down fashion, exploiting a single Deep Reactive Ion Etching (DRIE) Bosch process step (11) to form device channels. The channels consist of 350nm long vertical stacks of 4 nanowires on a slightly p-doped (~10 15 atoms/cm -3 ) SOI substrate.…”

Section: Device Fabricationmentioning

confidence: 99%

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

Marchi

Sacchetto

Frache

et al. 2012

2012 International Electron Devices Meeting

255

248

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We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show I on /I off > 10 6 and S 64mV/dec (70mV/dec) for p(n)-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.

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Section: Device Fabricationmentioning

confidence: 99%

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

Marchi

Sacchetto

Frache

et al. 2012

2012 International Electron Devices Meeting

255

248

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show abstract

“…Table I summarizes the fabrications process of the device along with the outcome of each step. The Bosch etching process [23] is utilized to form the device pattern. Gate dielectric is then formed by self-limiting oxidation which provides tiny oxide layer (≤ 5nm) around the channel.…”

Section: B Fabrication Processmentioning

confidence: 99%

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Mohammadi¹,

Gaillardon²,

Micheli³

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Controllable polarity silicon nanowire transistors are among the promising candidates to replace current CMOS in the near future owing to their superior electrostatic characteristics and advanced functionalities. From a circuit testing point of view, it is unclear if the current CMOS and Fin-FET fault models are comprehensive enough to model all defects of controllable polarity nanowires. In this paper, we deal with the above problem using inductive fault analysis on three-independent-gate silicon nanowire FETs. Simulations revealed that the current fault models, i.e. stuck-open faults, are insufficient to cover all modes of operation. The newly introduced test algorithm for stuck open can adequately capture the malfunction behavior of controllable polarity logic gates in the presence of nanowire break and bridge on polarity terminals.

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“…Table I summarizes the fabrications process of the device along with the outcome of each step. The Bosch etching process [31] is utilized to form the nanowire stack. An high-κ gate dielectric is then deposited over each patterned nanowire and provides a thin oxide layer (≤ 5 nm) around the channel.…”

Section: B Fabrication Processmentioning

confidence: 99%

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Mohammadi

Gaillardon

Micheli

2015

IEEE Trans. Nanotechnology

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Abstract-Controllable-polarity silicon nanowire transistors (CPSiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the online configuration of the device polarity. CP-SiNWFETs result in smaller and faster logic gates unachievable with conventional CMOS implementations. From a circuit testing point of view, it is unclear if the current CMOS and FinFET fault models are comprehensive enough to model all the defects of CP-SiNWFETs. In this paper, we explore the possible manufacturing defects of this technology through analyzing the fabrication steps and the layout structure of logic gates. Using the obtained defects, we then evaluate their impacts on the performance and the functionality of CP-SiNWFET logic gates. Out of the results, we extend the current fault model to a new a hybrid model, including stuck at p-type and stuck-at ntype, which can be efficiently used to test the logic circuits in this technology. The newly introduced fault model can be utilized to adequately capture the malfunction behavior of CP logic gates in the presence of nanowire break, bridge, and float defects. Moreover, the simulations revealed that the current CMOS test methods are insufficient to cover all faults, i.e., stuck-Open. We proposed an appropriate test method to capture such faults as well.Index Terms-Controllable-polarity silicon nanowires, defect, fault model, gate oxide short, nanotechnology.

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Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

Cited by 14 publications

References 20 publications

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

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