Nonvolatile and Volatile Memory Characteristics of a Silicon Nanowire Feedback Field-Effect Transistor With a Nitride Charge-Storage Layer

Kang, Hyungu; Cho, Jinsun; Kim, Yoonjoong; Lim, Doohyeok; Woo, Sola; Cho, Kyoungah

doi:10.1109/ted.2019.2924961

Cited by 18 publications

(28 citation statements)

References 17 publications

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“…The electrical characteristics of the FBFET have been investigated using the FBFET as a logic gate [10][11][12][13][14][15][16]. In addition, memory circuits, neuromorphic circuits, and biosensors consisting of FBFETs or hybrid components (e.g., the FBFET and the MOSFET) were investigated utilizing charging in the channel region and the hysteresis characteristics [17][18][19][20][21][22].…”

Section: Introductionmentioning

confidence: 99%

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation

2021

Micromachines

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In this study, we propose an improved macro-model of an N-type feedback field-effect transistor (NFBFET) and compare it with a previous macro-model for circuit simulation. The macro-model of the NFBFET is configured into two parts. One is a charge integrator circuit and the other is a current generator circuit. The charge integrator circuit consisted of one N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), one capacitor, and one resistor. This circuit implements the charging characteristics of NFBFET, which occur in the channel region. For the previous model, the current generator circuit consisted of one ideal switch and one resistor. The previous current generator circuit could implement IDS-VGS characteristics but could not accurately implement IDS-VDS characteristics. To solve this problem, we connected a physics-based diode model with an ideal switch in series to the current generator circuit. The parameters of the NMOSFET and diode used in this proposed model were fitted from TCAD data of the NFBFET, divided into two parts. The proposed model implements not only the IDS-VGS characteristics but also the IDS-VDS characteristics. A hybrid inverter and an integrate and fire (I&F) circuit for a spiking neural network, which consisted of NMOSFETs and an NFBFET, were simulated using the circuit simulator to verify a validation of the proposed NFBFET macro-model.

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Section: Introductionmentioning

confidence: 99%

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation

2021

Micromachines

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“…Therefore, it can be used as a logic and memory device with the same structure. Various applications of FBFET were studied, such as using it as a logic device, a memory device, and a neuron circuit [ 24 , 25 , 26 , 27 , 28 , 29 , 30 ]. In the previous study, we investigated electrical coupling between vertically stacked FBFETs in the monolithic 3-dimensional inverter (M3DINV) with FBFETs, in terms of device characteristics [ 31 ].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

2020

Micromachines

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The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

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“…In a logic-in-memory computing system, the memory and logic operations are merged in a single basic device structure 20,21 . Accordingly, the logic-in-memory computing system can substantially reduce the power consumption and circuit density.Recently, feedback field-effect transistors (FBFETs) have opened up the possibilities for logic-in-memory computing systems owing to their switchable-memory characteristics [22][23][24][25][26][27] . FBFETs are one of the novel FETs that allow the applications in both ternary logic and logic-in-memory computing systems.…”

mentioning

confidence: 99%

“…Recently, feedback field-effect transistors (FBFETs) have opened up the possibilities for logic-in-memory computing systems owing to their switchable-memory characteristics [22][23][24][25][26][27] . FBFETs are one of the novel FETs that allow the applications in both ternary logic and logic-in-memory computing systems.…”

mentioning

confidence: 99%

New ternary inverter with memory function using silicon feedback field-effect transistors

Son

Cho

Kim

2022

Sci Rep

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In this study, we present a fully complementary metal–oxide–semiconductor-compatible ternary inverter with a memory function using silicon feedback field-effect transistors (FBFETs). FBFETs operate with a positive feedback loop by carrier accumulation in their channels, which allows to achieve excellent memory characteristics with extremely low subthreshold swings. This hybrid operation of the switching and memory functions enables FBFETs to implement memory operation in a conventional CMOS logic scheme. The inverter comprising p- and n-channel FBFETs in series can be in ternary logic states and retain these states during the hold operation owing to the switching and memory functions of FBFETs. It exhibits a high voltage gain of approximately 73 V/V, logic holding time of 150 s, and reliable endurance of approximately 105. This ternary inverter with memory function demonstrates possibilities for a new computing paradigm in multivalued logic applications.

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Nonvolatile and Volatile Memory Characteristics of a Silicon Nanowire Feedback Field-Effect Transistor With a Nitride Charge-Storage Layer

Cited by 18 publications

References 17 publications

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

New ternary inverter with memory function using silicon feedback field-effect transistors

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