Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps

Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages

“…This is because a small misalignment of chip position can potentially result in insufficient support from either the top or bottom surface of the chip [4,17], and subsequently leads to warpage. In additional, the CTE mismatch between silicon and copper-filled TSVs can also induce thermo-mechanical stress, leading to material deformation, delamination and cracking in the packaged chip [5][6].…”

“…The fabrication process of a complete packaged IC is a tricky one, as it involves the use of different materials of distinct coefficients of thermal expansion (CTEs), e.g. die bond pad, die attach adhesive/epoxy glue, moulding compounds and Cu-filled through-silicon-vias (TSVs) [2][3][4][5][6]. Thermal stress and warpage are frequently generated in the packaged chip during the thermal processing steps as a consequence of the CTE mismatch of these materials [7][8][9][10][11].…”

Experimental measurement of the effect of copper through-silicon via diameter on stress buildup using synchrotron-based X-ray source

“…However, with the exception of the synchrotronbased experimental studies done by [6,12], most of the stress analysis studies related to the effect of Cu TSV diameter in the open literature, have been based on finite element analysis (FEA) [13][14][15][16][17]. While the experimental & Chukwudi Okoro chukwudi.okoro@nist.gov study in [12] compared the stresses in Cu for two different Cu TSV diameters, it was impossible to directly compare the results, because the samples used were from different manufacturers and had different process histories.…”

Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias

“…Due to the mismatch in the coefficients of thermal expansion (CTEs) of the via materials and Si, thermal stresses are ubiquitously induced during processing and thermal cycling of TSV structures, which can potentially degrade the performance of stress-sensitive devices around the TSVs [8,9] or drive crack growth in 3-D interconnects [9][10][11][12][13]. Therefore, the success of 3-D integration largely relies on the characteristics of thermo-mechanical stresses developed in the system and its impact on performance and reliability.…”

“…Therefore, the success of 3-D integration largely relies on the characteristics of thermo-mechanical stresses developed in the system and its impact on performance and reliability. Finite element methods have been used to numerically analyze the thermo-mechanical stresses in 3-D integrated structures [9][10][11][12][13], typically complicated by specific material processes and structural designs. To assess the themo-mechanical reliability of TSV structures, the driving forces for both cohesive and interfacial crack growth were calculated [12,13].…”