Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps

Selvanayagam, Cheryl; Lau, John H.; Zhang, Xiaowu; Seah, S.K.W.; Kripesh, V.; Chai, Tai Chong

doi:10.1109/tadvp.2009.2021661

Cited by 247 publications

(68 citation statements)

References 5 publications

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“…However, due to the mismatch in the coefficient of thermal expansion (CTE) between the via materials and Si, thermal stresses are ubiquitously induced during processing and thermal cycling of TSV structures [4], [5]. The thermal stresses can drive interfacial delamination between the TSV and the Si matrix, resulting in the TSV "popup" to damage the on-chip wiring structures [6]- [9]. The stress induced by TSV can also affect the carrier mobility due to the piezoresistivity effect to degrade the performance of the MOSFET devices [10]- [12].…”

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confidence: 99%

Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Ryu

Jiang

et al. 2012

IEEE Trans. Device Mater. Relib.

107

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Abstract-Three-dimensional (3-D) integration with throughsilicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in the TSV structures can affect the device performance by degrading carrier mobility and raise serious reliability concerns. In this paper, the effect of thermal stresses in TSV structures on carrier mobility and keep-out zone (KOZ) was investigated by focusing on the characteristics of the stresses near the surface where the electronic devices are located. The near-surface stresses were characterized by finite element analysis, and the stress effect on carrier mobility was evaluated by considering the piezoresistivity effect near the Si surface. In this paper, the elastic anisotropy of Si was taken into account to evaluate the effect on carrier mobility for both n-and p-channel MOSFET devices aligned along the [100] and [110] directions. The results showed a significant stress effect on carrier mobility, particularly for n-type Si with [100] device alignment and p-type Si with [110] device alignment. Based on these results, the dimension of the KOZ was estimated based on a criterion of 5% change in the carrier mobility. Finally, the effects due to stress interactions in a TSV array and plasticity in Cu vias on the KOZ were investigated. The effect of stress interaction was found to depend on the ratio of the pitch to diameter of the TSV array. When this ratio is less than 5, the stress interaction can increase the size of the KOZ. In contrast, the via material plasticity was found to be useful in reducing the stress level and hence the size of the KOZ.Index Terms-Finite element analysis (FEA), keep-out zone (KOZ), thermomechanical reliability, through-silicon via (TSV), three-dimensional interconnects.

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confidence: 99%

Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Ryu

Jiang

et al. 2012

IEEE Trans. Device Mater. Relib.

107

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“…However, the mismatch in the coefficients of thermal expansion (CTEs) between Cu and Si is relatively large, which is responsible for the development of thermal stresses in the TSV structures. The thermal stresses can arise during fabrication, testing and service of the TSVs, leading to various reliability issues, such as crack growth, via extrusion, and degradation of device performance [1][2][3][4]. Therefore, it is important to experimentally characterize the thermal stresses and understand their impact on TSV reliability for development of 3-D interconnects.…”

Section: Introductionmentioning

confidence: 99%

Thermomechanical characterization and modeling for TSV structures

Jiang

Ryu

Zhao

et al. 2014

AIP Conference Proceedings

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Abstract. Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future technology requirements. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper presents experimental measurements of the thermal stresses in TSV structures and analyses of interfacial reliability. The micro-Raman measurements were made to characterize the local distribution of the near-surface stresses in Si around TSVs. On the other hand, the precision wafer curvature technique was employed to measure the average stress and deformation in the TSV structures subject to thermal cycling. To understand the elastic and plastic behavior of TSVs, the microstructural evolution of the Cu vias was analyzed using focused ion beam (FIB) and electron backscattering diffraction (EBSD) techniques. Furthermore, the impact of thermal stresses on interfacial reliability of TSV structures was investigated by a shear-lag cohesive zone model that predicts the critical temperatures and critical via diameters.

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“…Owing to the large difference in coefficients-of-thermal-expansion (CTE) of the copper TSVs and that of the silicon [5], however, tensile stress inevitably appears on the silicon [6]. Such thermal-mechanical stress is likely to cause TSV interfacial cracks (see Fig.…”

Section: Introductionmentioning

confidence: 99%

On effective and efficient in-field TSV repair for stacked 3D ICs

Jiāng

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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Three-dimensional (3D) integration based on through-silicon-vias (TSVs) is rapidly gaining traction for industry adoption. However, manufacturing processes for TSVs have been shown to introduce new failure mechanisms. In particular, thermo-mechanical stress and electromigration introduce reliability threats for TSVs, e.g., voids and interfacial cracks, which can lead to hard-to-predict timing errors on critical paths with TSVs, thereby resulting in accelerated chip failure in the field. Burn-in for screening latent defects during manufacturing is expensive and its effectiveness for new TSV defect types has yet to be thoroughly characterized. We describe a reconfigurable in-field repair solution that is able to effectively tolerate latent TSV defects through the judicious use of spares. The proposed solution includes a reconfigurable repair architecture that enables spare TSV sharing between TSV grids, and the corresponding in-field repair algorithms. The effectiveness and efficiency of our proposed solution is evaluated using 3D benchmark designs.

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Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps

Cited by 247 publications

References 5 publications

Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Thermomechanical characterization and modeling for TSV structures

On effective and efficient in-field TSV repair for stacked 3D ICs

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