Nonconvex Gate Delay Modeling and Delay Optimization

Tennakoon, Hiran; Sechen, Carl

doi:10.1109/tcad.2008.927758

Cited by 16 publications

(7 citation statements)

References 17 publications

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“…We assume 20% process variations for all gate sizes around their nominal values. An convex optimization software [12] was used to solve the final GP problem generalized in (25). The optimization objective is to minimize the total area i α i x i , where α i denotes the number of transistors in gate i, and gate size x i stands for the ratio of area of gate i to that of a minimum sized inverter.…”

Section: Resultsmentioning

confidence: 99%

“…As pointed out in [25], signomial models can be more accurate to estimate gate delays. As opposed to posynomials, there are no restrictions on the sign of the multiplicative coefficients in signomials.…”

Section: Discussionmentioning

confidence: 99%

“…As opposed to posynomials, there are no restrictions on the sign of the multiplicative coefficients in signomials. Posynomial in fact is a special case of signomial, and signomial delay models achieve better fits to SPICE generated data [25]. However, signomials are not convex in general.…”

Section: Discussionmentioning

confidence: 99%

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Robust gate sizing by Uncertainty Second Order Cone

Sun

Wang

2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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The accuracy of estimation of gate sizing variations becomes a dominant factor in automation design of transistor gate sizing. This paper proposes a new Uncertainty Second Order Cone (USOC) estimation model, which is applied to optimize the gate sizes considering random parameters variations and circuit uncertainties. Different from present researcher's favorite Uncertainty Ellipsoid (UE) method of random variation estimation, USOC model imposes no requirement on parameter correlations and no prerequisite on their distributions. This important advantage extends USOC model to more general applications with more accuracy. With parameter variations characterized in USOC representation, the robust gate sizing problem can be conveniently formulated into a standard Geometric Program (GP), which can be efficiently solved by convex optimization techniques. Experimental results on ISCAS benchmark circuit show that the new estimation model improves the accuracy of gate sizing problem by up to 21% compared with UE method.

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Section: Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

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Robust gate sizing by Uncertainty Second Order Cone

Sun

Wang

2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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“…We claim that a local selection is fast and efficient since the gate delay has major impact only on its first level of fanins and fanouts and the circuit arrival times (which have a global dependency) were eliminated from the formulation through KKT conditions. Our algorithm obtained better convergence by combining the scheduling of a power weighting factor [Tennakoon and Sechen 2002] and the modified subgradient method [Tennakoon and Sechen 2008] for the first time in the discrete domain.…”

Section: Contributions Of This Workmentioning

confidence: 99%

“…The main advantage of optimizing within the continuous space is that it allows the use of consolidated optimization methods, that provide high-quality and efficient solutions [Boyd and Vandenberghe 2004]. Among the techniques assuming continuous parameters the following ones deserve to be highlighted: -sensitivity-based heuristics [Fishburn and Dunlop 1985;Srivastava et al 2004]; -Lagrangian relaxation combined with dynamic programming [Rahman et al 2011], or with greedy local sizing [Chen et al 1999;Hsinwei et al 2005;Tennakoon and Sechen 2008]; -linear programming applied to piecewise linear delay models [Berkelaar and Jess 1990] or for slack allocation [Nguyen et al 2003]; -convex optimization techniques [Kasamsetty et al 2000;Roy et al 2007]. …”

Section: Related Workmentioning

confidence: 99%

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

Livramento

Guth

Güntzel

et al. 2014

ACM Trans. Des. Autom. Electron. Syst.

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Discrete gate sizing has attracted a lot of attention recently as the EDA industry faces the challenge of optimizing large standard cell-based circuits. The discrete nature of the problem, along with complex timing models, stringent design constraints, and ever-increasing circuit sizes, make the problem very difficult to tackle. Lagrangian Relaxation (LR) is an effective technique to handle complex constrained optimization problems and therefore has been successfully applied to solve the gate sizing problem. This article proposes an improved Lagrangian relaxation formulation for discrete gate sizing that relaxes timing, maximum gate input slew, and maximum gate output capacitance constraints. Based on such formulation, we propose a hybrid technique composed of three steps. First, a topological greedy heuristic solves the LR formulation. Such a heuristic is applied assuming a slightly increased target clock period (backoff factor) to better explore the solution space. Second, a delay recovery heuristic reestablishes the original target clock with small power overhead. Third, a power recovery heuristic explores the remaining slacks to further reduce power. Experiments on the ISPD 2012 Contest benchmarks show that our hybrid technique provides less leakage power than the state-of-the-art work for every circuit from the ISPD 2012 Contest infrastructure, achieving up to 24% less leakage. In addition, our technique achieves a much better compromise between leakage reduction and runtime, obtaining, on average, 9% less leakage power while running 8.8 times faster. ACM Reference Format: Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel, and Marcelo O. Johann. 2014. A hybrid technique for discrete gate sizing based on lagrangian relaxation.

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