Robust gate sizing by Uncertainty Second Order Cone

Abstract

The accuracy of estimation of gate sizing variations becomes a dominant factor in automation design of transistor gate sizing. This paper proposes a new Uncertainty Second Order Cone (USOC) estimation model, which is applied to optimize the gate sizes considering random parameters variations and circuit uncertainties. Different from present researcher's favorite Uncertainty Ellipsoid (UE) method of random variation estimation, USOC model imposes no requirement on parameter correlations and no prerequisite on their distributions. This important advantage extends USOC model to more general applications with more accuracy. With parameter variations characterized in USOC representation, the robust gate sizing problem can be conveniently formulated into a standard Geometric Program (GP), which can be efficiently solved by convex optimization techniques. Experimental results on ISCAS benchmark circuit show that the new estimation model improves the accuracy of gate sizing problem by up to 21% compared with UE method.

Transistor size optimization in digital circuits using ant colony optimization for continuous domain

“…This algorithm efficiently optimizes transistor-level sizing in VLSI circuits to omit the issue of temporal performance degradation due to negative bias temperature instability. In another approach [10], a new uncertainty second-order cone (USOC) estimation model is proposed to optimize the gate sizes under process variations. It defines parameter variations in USOC representation and formulates sizing problem into a standard geometric program, which is then, solved by convex optimization techniques.…”