Transistor size optimization in digital circuits using ant colony optimization for continuous domain

Gupta, Himanshu; Ghosh, Bahniman

doi:10.1002/cta.1879

Cited by 14 publications

(7 citation statements)

References 18 publications

(37 reference statements)

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“…They depend on many factors, including transistor threshold voltages [1] and the symmetry of the pMOS vs. nMOS stack. Since varying these parameters is commonly used in advanced circuit design to trade delay for power consumption [6,11] and reliability [7], as well as for implementing special gates (e.g. logic-level conversion [12]), the range of suitable discretization threshold voltages could differ significantly among gates.…”

Section: Discretization Threshold Voltagesmentioning

confidence: 99%

A Composable Glitch-Aware Delay Model

Maier

Öhlinger

Schmid

et al. 2021

Proceedings of the 2021 Great Lakes Symposium on VLSI

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We introduce the Composable Involution Delay Model (CIDM) for fast and accurate digital simulation. It is based on the Involution Delay Model (IDM) [Függer et al., IEEE TCAD 2020], which has been shown to be the only existing candidate model for faithful glitch propagation. The IDM, however, has shortcomings that limit its applicability. Our CIDM thus reduces the characterization effort by allowing independent discretization thresholds, improves composability and increases the modeling power by exposing canceled pulse trains at the gate interconnect. We formally show that, despite these improvements, the CIDM still retains the IDM's faithfulness.

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Section: Discretization Threshold Voltagesmentioning

confidence: 99%

A Composable Glitch-Aware Delay Model

Maier

Öhlinger

Schmid

et al. 2021

Proceedings of the 2021 Great Lakes Symposium on VLSI

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“…They emphasized the need for careful selection of V DD and transistor upsizing for minimizing energy consumption. Gupta and Ghosh used ant colony for optimizing transistor sizes of (a rather dated) technology node of 180 nm.…”

Section: Extending the Transistor Channel Lengthmentioning

confidence: 99%

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

Beg

2014

Circuit Theory & Apps

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Summary This paper presents an automatic method for sizing the transistors in CMOS gates. The method utilizes a feedback control system to efficiently optimize the transistor sizes in small and large fan‐in gates, with the primary goal of enhancing noise robustness (as characterized by the static noise margin). The gates retain their robustness under threshold‐voltage variations over a range of supply voltages. The optimized gates not only expend reduced power and energy, but also take up less area than the conventional ones. These multi‐faceted gains, however, do incur some performance loss. Copyright © 2014 John Wiley & Sons, Ltd.

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“…Also, not much effort has been shown in the existing literature to design CMOS circuits with leakage power constraints in the approximation methodology. At deep sub-micron regimes, the static power becomes comparable with the dynamic power [5] [13] [17], and has become a dominant component of power dissipation, limiting the performance of the circuits. This is crucial to low power approximate designs where power management is of substantial importance in areas pertaining to battery lifetime in edge computing, smartphones, etc.…”

Section: Introductionmentioning

confidence: 99%

Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence

Saha

Ahmed

Kalluru

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper proposes low power optimization using a modified swarm intelligence algorithm for the scenariostransistor sizing based static power reduction and low power standard cell generation for approximate computing. In these scenarios, we explore a lower abstraction level and see how standard cells can be tuned to a power-delay-quality optimal point. For transistor sizing, the algorithm considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55 o C to 125 o C) and supply voltage (±10%) variations to yield PVT aware robust sizing solutions. The approach has been applied on numerous single and multistage circuits (including ISCAS benchmarks) while proposing a dual sizing solution for non-critical and critical path cells. For approximate systems, we present algorithm-generated full adder designs for speech processing systems. The designs vary in terms of accuracy and power. Results show leakage reductions up to 58.2% for conventional and 66.8% with approximation designs for 22nm metal gate high-K (MGK) technology cells.

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Transistor size optimization in digital circuits using ant colony optimization for continuous domain

Cited by 14 publications

References 18 publications

A Composable Glitch-Aware Delay Model

A Composable Glitch-Aware Delay Model

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence

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