Non-Uniform "Fat-Meshes" for Chip Multiprocessors

Abstract

This paper studies the traffic hot spots of mesh networks in the context of chip multiprocessors. To mitigate these effects, this paper describes a non-uniform fat-mesh extension to mesh networks, which are popular for chip multiprocessors. The fat-mesh is inspired by the fat-tree and dedicates additional links for connections with heavy traffic (e.g. near the center) with fewer links for lighter traffic (e.g. near the periphery). Two fat-mesh schemes are studied based on the traffic requirements of chip multiprocessors using dimensional ordered XY routing and a randomized XY-YX routing algorithms, respectively. Analytical fat-mesh models are constructed by theoretically presenting the expressions for the traffic requirements of personalized all-to-all traffic for both the raw message numbers and their normalized equivalents. We demonstrate how traffic scales for a traditional mesh compared to a non-uniform fat mesh. Simulation results demonstrate that using same number of physical links the non-uniform fat-mesh can achieve better performance than a uniform fat-mesh mesh using both synthetic traffic patterns and splash-2 benchmark traces.

An analytical model for on-chip interconnects in multimedia embedded systems

“…A number of recent studies have convincingly shown that multimedia applications can be supported in on-chip interconnects [Lee et al 2006;Ogras and Marculescu 2008;Varatkar and Marculescu 2004]. Furthermore, the message designations often exhibit the nonuniform distributions over on-chip interconnects [Mirza-Aghatabar et al 2007;Zhang and Jones 2009].…”