Noise-induced error rate as limiting factory for energy per operation in digital ICs

Stein, K. U.

doi:10.1109/jssc.1977.1050947

Cited by 46 publications

(31 citation statements)

References 7 publications

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“…We consider a contamination error when there is a misleading of the logic level, this means that the "1" voltage level crosses down the half power supply level threshold (1 is understood as 0) or that the "0" voltage level crosses up the half power supply level threshold (0 is understood as 1). The probability of (through VDD and GND) of contamination noise errors are given by: Similar reasoning for the level contamination error and probability calculation can be found in [11] and [12]. Figure 5 shows the representation of equation (4) for different levels of noise amplitude (typical deviation) relative to VDD, σ vdd /V DD .…”

Section: Logic Level Contamination Errormentioning

confidence: 81%

Power supply noise and logic error probability

Andrade

Martorell

Pons

et al. 2007

2007 18th European Conference on Circuit Theory and Design

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Abstract-Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays and a noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in this paper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanisms and shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.

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Section: Logic Level Contamination Errormentioning

confidence: 81%

Power supply noise and logic error probability

Andrade

Martorell

Pons

et al. 2007

2007 18th European Conference on Circuit Theory and Design

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“…For a small 1 1F capacitor, the rms noise level is roughly 2 mV. However, because of a trend of larger interconnect capacitances, large digital buffers, and higher operating temperatures due to transistor density, thermal noise has been shown to increase to 200 mV in even nanoscale digital circuits [5]. In lowpower digital logic, a supply voltage in the hundreds of mV is not unreasonable especially in subthreshold logic and hence the probability of an error becomes exceedingly likely in this case [3].…”

Section: Mosfet Implementation and Device Propertiesmentioning

confidence: 99%

“…Indeed a fundamental limit to voltage scaling technology has been proposed: the thermodynamic limit of these devices [4]. When the supply voltage becomes comparable to thermal noise levels in these types of ultra-low power designs, devices start to behave probabilistically giving an incorrect output with some nonzero probability [4,5]. Kish predicts that the thermal noise phenomenon will result in the "death" of Moore's law [6].…”

Section: Introductionmentioning

confidence: 99%

Error Immune Logic for Low-Power Probabilistic Computing

et al. 2010

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Two novel theorems are developed which prove that certain logic functions are more robust to errors than others. These theorems are used to construct datapath circuits that give an increased immunity to error over other naive implementations. A link between probabilistic operation and ultra-low energy computing has been shown in prior work. These novel theorems and designs will be used to further improve probabilistic design of ultra-low power datapaths. This culminates in an asynchronous design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25 μm technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case.

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“…In the case of digital circuits this voltage fluctuation causes a fluctuation in the propagation delay that is a cause of performance degradation. This could imply an error probability of 10 -14 in every atomic processing cycle in the year 2020, according to [16]. New design strategies towards the reduction of transitions and even the implementation of clock-less circuits (asynchronous) are being developed.…”

Section: Low Voltage Designmentioning

confidence: 99%

“…In [16], the error rate caused by thermal noise for a given energy operation was investigated. Figure 5 shows this relation, taken from [16], and the vertical arrow indicates the energy corresponding to the CMOS technology in 2020. This implies an error rate of 10 -28…”

Section: Thermal Noise Impactmentioning

confidence: 99%

Electronic System Design Paradigms in the Technologies of the Year 2020

García¹,

Moll²,

Rubio³

2010

Int.J.Soc.Mater.Eng.Resour.

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This paper analyses the evolution of late and beyond CMOS technologies showing the relevant effect on the electronic design methods and rules due to the dramatic reduction of quality of the manufactured components. The paper argues that the main impact on such future technologies will be caused by the increase of the manufacturing defect ratio of components and circuits, the reduction of reliability through a huge increase of the error ratio and a drastic drop of the components quality. Consequently, new strategies of design have to be considered, among them the hierarchical fault tolerance that is presented in the paper. This fact will have implications in the design rules as we know them today.

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Noise-induced error rate as limiting factory for energy per operation in digital ICs

Cited by 46 publications

References 7 publications

Power supply noise and logic error probability

Power supply noise and logic error probability

Error Immune Logic for Low-Power Probabilistic Computing

Electronic System Design Paradigms in the Technologies of the Year 2020

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