Error Immune Logic for Low-Power Probabilistic Computing

Abstract

Two novel theorems are developed which prove that certain logic functions are more robust to errors than others. These theorems are used to construct datapath circuits that give an increased immunity to error over other naive implementations. A link between probabilistic operation and ultra-low energy computing has been shown in prior work. These novel theorems and designs will be used to further improve probabilistic design of ultra-low power datapaths. This culminates in an asynchronous design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25 μm technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case.

Mathematical estimation of logical masking capability of majority/minority gates used in nanoelectronic circuits

“…GEMNIF and GEMFIC. As mentioned in [29] that not all gates created are equal, it is found that gate types with a singleton ON-set or OFF-set (AND, NAND, OR, NOR) exhibit greater fault tolerance i.e. have less GEMNIF and GEMFIC values when compared to gate types (XOR, XNOR, Majority, Minority) which feature identical ON-set and OFF-set cardinalities.…”

“…References [29]- [32] analyzed the impact of probabilistic input errors on the outputs of some logic gates and some logic circuits. Reference [33] analyzed the logical masking capability of conventional gates such as NOT (i.e.…”

A fast simulator for the analysis of sub-threshold thermal noise transients

“…In recent years, there have been several efforts to address the design of thermal-noise-tolerant circuit architectures [5,6,13,16]. All these works modeled the thermal noise by scaling the noise standard deviation up to a value that would allow a SET to be observed more easily in the logic circuits.…”

On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design

“…Let us consider an exemplar 2-input OR gate to get an insight into fault-tolerance analysis based on the model put forward in [4]. Table 1 shows the truth table of the 2-input OR gate, highlighting possible errors that might occur in the inputs and their subsequent impact on the output.…”

“…Note that the cardinality of ON and OFF-sets of XOR and XNOR gates are equal, while AND, NAND, OR and NOR gates have unequal ON and OFF-set dimensions. Bo Marr et al [4] did a preliminary work on error immune analysis of basic logic gates and proposed two theorems: (i) gates whose ON-set or OFF-set cardinality is singleton have minimal error probability, and (ii) error propagation increases with increase in a circuit's logic depth. It is found that the latter axiom would hold good for combinational logic circuits constructed using AND/NAND, OR/NOR gate types, while circuits featuring only XOR/XNOR gate types would have similar output error probabilities regardless of the number of logic levels.…”