Noise in Semiconductor Devices

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

2013

127

Abstract-Physically Unclonable Functions (PUFs) are emerging as hardware security primitives. For so-called strong PUFs, the number of challenge-response pairs (CRPs) increases exponentially with the required chip area in the ideal case. They can provide a mechanism to authenticate chips which is inherently unique for every manufactured sample. Modeling of the CRP behavior through Machine Learning (ML) has shown to be a threat however. In this paper, we exploit repeatability imperfections of PUF responses as a side channel for model building. We demonstrate that 65nm CMOS arbiter PUFs can be modeled successfully, without utilizing any ML algorithm. Data originates from real-world measurements and hence not from simulations. Modeling accuracies exceeding 97% are obtained, which is comparable with previously published ML results. Information leakage through the exploited side channel should be considered for all strong PUF designs. Combined attack strategies, whereby repeatability measurements facilitate ML, might be effective and are recommended for further research.

Section: Variability and Noisementioning

confidence: 99%

Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

2013

127

“…Random Dopant Fluctuation and Line-Edge/Width Roughness are important sources of variability for CMOS devices [7]. White thermal noise and 1/f noise affect the CMOS channel current [6]. Interconnect is affected by Line-Edge/Width Roughness and white thermal noise too.…”

Section: Variability and Noisementioning

confidence: 99%

Fault Injection Modeling Attacks on 65 nm Arbiter and RO Sum PUFs via Environmental Changes

IEEE Trans. Circuits Syst. I

2014

102

Abstract. Physically Unclonable Functions (PUFs) are emerging as hardware security primitives. So-called strong PUFs provide a mechanism to authenticate chips which is inherently unique for every manufactured sample. To prevent cloning, modeling of the challenge-response pair (CRP) behavior should be infeasible. Machine learning (ML) algorithms are a well-known threat. Recently, repeatability imperfections of PUF responses have been identified as another threat. CMOS device noise renders a significant fraction of the CRPs unstable, hereby providing a side channel for modeling attacks. In previous work, 65nm arbiter PUFs have been modeled as such with accuracies exceeding 97%. However, more PUF evaluations were required than for state-of-the-art ML approaches. In this work, we accelerate repeatability attacks by increasing the fraction of unstable CRPs. Response evaluation faults are triggered via environmental changes hereby. The attack speed, which is proportional to the fraction of unstable CRPs, increases with a factor 2.4 for both arbiter and ring oscillator (RO) sum PUFs. Data originates from a 65nm silicon chip and hence not from simulations.

“…The main responsible is noise in CMOS transistors (and interconnect), to be considered as a random time-dependent phenomenon [5]. Its presence is unavoidable.…”

Section: Puf Imperfectionsmentioning

confidence: 99%

Attacking PUF-Based Pattern Matching Key Generators via Helper Data Manipulation

Topics in Cryptology – CT-RSA 2014

2014

Abstract. Physically Unclonable Functions (PUFs) provide a unique signature for integrated circuits (ICs), similar to a fingerprint for humans. They are primarily used to generate secret keys, hereby exploiting the unique manufacturing variations of an IC. Unfortunately, PUF output bits are not perfectly reproducible and non-uniformly distributed. To obtain a high-quality key, one needs to implement additional post-processing logic on the same IC. Fuzzy extractors are the well-established standard solution. Pattern Matching Key Generators (PMKGs) have been proposed as an alternative. In this work, we demonstrate the latter construction to be vulnerable against manipulation of its public helper data. Full key recovery is possible, although depending on system design choices. We demonstrate our attacks using a 4-XOR arbiter PUF, manufactured in 65nm CMOS technology. We also propose a simple but effective countermeasure.