Noise in self-timed and synchronous implementations of a DSP

Lien, W.A.; Day, P.; Farnsworth, C.; Glibbery, Ronald; Jackson, D.L.; Liu, J.; Paver, N.C.; Chappel, J.; Kozma, L.

doi:10.1109/rawcon.1998.709140

Cited by 4 publications

(3 citation statements)

References 10 publications

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“…Self-timed circuits also have better electromagnetic compatibility [8] and noise susceptibility attributes compared to synchronous designs [9], consume power only where and when active [10,11], and feature excellent design reusability [12]. Moreover, self-timed circuits are self-checking [13,14] and are latency insensitive thus being naturally elastic or adaptive.…”

Section: Vlsi Designmentioning

confidence: 99%

Redundant Logic Insertion and Latency Reduction in Self‐Timed Adders

2012

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A novel concept of logic redundancy insertion is presented that facilitates significant latency reduction in self-timed adder circuits. The proposed concept is universal in the sense that it can be extended to a variety of self-timed design methods. Redundant logic can be incorporated to generate efficient self-timed realizations of iterative logic specifications. Based on the case study of a 32-bit self-timed carry-ripple adder, it has been found that redundant implementations minimize the data path latency by 21.1% at the expense of increases in area and power by 2.3% and 0.8% on average compared to their nonredundant counterparts. However, when considering further peephole logic optimizations, it has been observed in a specific scenario that the delay reduction could be as high as 31% while accompanied by only meager area and power penalties of 0.6% and 1.2%, respectively. Moreover, redundant logic adders pave the way for spacer propagation in constant time and garner actual case latency for addition of valid data.

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Section: Vlsi Designmentioning

confidence: 99%

Redundant Logic Insertion and Latency Reduction in Self‐Timed Adders

2012

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“…• Higher speed because of the average case performance versus worst case in synchronous circuits [1,2] • Less power consumption due to the absence of clock trees and natural support of idle mode [3,4] • Low EMI and noise due to even distribution of switching activity in time [5,6] Nevertheless, the few success stories did little to change the public acceptance of asynchronous approaches. In the current design landscape, asynchronous methodologies are considered either as exotic (an optimistic opinion from academia) or as non-observable (a pessimistic opinion from industry).…”

Section: Introductionmentioning

confidence: 99%

Testing of asynchronous designs by "inappropriate" means. Synchronous approach

Kondratyev

Sorensen²,

Streich³

Proceedings Eighth International Symposium on Asynchronous Circuits and Systems

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“…Recent investigations [19] show that by a self-timed approach one might reduce not only simultaneous switching noise, but also the high frequency components of noise (400% reduction for peak switching current [19]) and Electro-Magnetic Interference by an order of magnitude with respect to a comparable synchronous design.…”

Section: Introductionmentioning

confidence: 99%

Behavioral transformations to increase noise immunity in asynchronous specifications

Taubin

Kondratyev²,

Cortadella³

et al.

Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems

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Noise immunity is becoming one of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the problems originated by simultaneous switching noise. However, they are also more sensitive than synchronous ones to spurious signal transitions and delay variations produced by crosstalk noise. This paper addresses the problem of analyzing and synthesizing asynchronous circuits with noise immunity being the main design parameter. The techniques presented in the paper focus on cross talk noise and tackle the problem from the behavioral point of view.

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Noise in self-timed and synchronous implementations of a DSP

Cited by 4 publications

References 10 publications

Redundant Logic Insertion and Latency Reduction in Self‐Timed Adders

Redundant Logic Insertion and Latency Reduction in Self‐Timed Adders

Testing of asynchronous designs by "inappropriate" means. Synchronous approach

Behavioral transformations to increase noise immunity in asynchronous specifications

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