Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling

Abstract

This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constraints have led microprocessor designers to incorporate aggressive power saving techniques such as clock-gating, that place a significant burden on the power delivery network. While the application of extensive clock-gating can effectively reduce power consumption, unfortunately, it can also induce large inductive noise (di/dt), resulting in signal integrity and reliability issues. To combat these problems, processors are usually designed for the worst-case current consumption scenario using adequate supply voltage and decoupling capacitances.To tackle high-frequency inductive noise and potential IR drops, we propose a novel design methodology that integrates microarchitectural profiling feedback into the floorplanning process. We present two microarchitectural metrics to quantify the noise susceptibility of a module:self weighting and correlation weighting. By using these metrics in a force-directed floorplanning algorithm to assign power pin affinity to modules, we can quickly converge to a design for average-case current consumption. By designing for the average-case and employing dynamic di/dt control for the worst-case, we can ensure that a chip is noise-tolerant without exceeding decap budget constraints. Our observations showed that certain functional modules in a processor exhibit consistent and highly correlated switching activity, that can be used to guide module placement distance from power pins. The experimental results demonstrate that the force-directed floorplanning technique can effectively suppress supply noise experienced by modules, reduce the total number of supply-noise margin violations, and achieve a floorplan with considerably lower IR drop, as compared to a wire-length driven floorplan.

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

“…Most of these techniques tried to reduce the impedance path to individual modules in a processor, minimizing the voltage surges and dips. Floorplanning algorithms with the objective of minimizing inductive noise were studied recently [5,6,18]. Unlike this work, they are completely static solutions.…”

“…Note that simultaneous switching events along the same direction raises a major issue to power delivery. A floorplan that is resistant to inductive noise tries to generate a well balanced layout to distribute the current demand in a more regular manner across the power-supply grid [5,6,18]. Nonetheless, floorplanning is a static solution.…”

Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation

“…In contrast, our work demonstrates minimization of power-supply noise for the entire architecture and chip, and could be used in concert with their technique. The only other prior effort that includes early-design-phase consideration of power-supply noise [Mohamood et al 2007] does not directly consider the use of a dynamic controller. A comparison to this work is included in Section 6.…”

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise

“…Tight low power requirements have forced MPSoC to aggressively adopt low power techniques such as dynamic voltage/frequency scaling, clock gating, and power gating [1,2]. While low power techniques like power gating can dramatically reduce power consumption for idle processing units (PUs), they exacerbate simultaneous switching noise (or di/dt noise) on the power delivery network.…”

“…The proposed techniques include sleep transistor designs [3,4], decoupling capacitor insertion [5], and P/G noise-aware floorplanning [1,2,6]. Recently, power gating sequence scheduling [7][8][9] in a block or several blocks were proposed to tradeoff wake-up time for P/G noise reduction.…”