NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication

Krishna, Tushar; Kumar, Amit; Chiang, Patrick; Erez, Mattan; Peh, Li-Shiuan

doi:10.1109/hoti.2008.22

Cited by 56 publications

(37 citation statements)

References 17 publications

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“…Express virtual channels [14] and token flow-control [13] allow the whole router pipeline to be bypassed. Further work has proposed using global lines to broadcast control information and arbitrate among different express virtual channels [12]. More optimizations have been explored such as dynamic VC buffer allocation and other aspects, such as fault-tolerance [9,21].…”

Section: Related Workmentioning

confidence: 99%

Router designs for elastic buffer on-chip networks

Dally

2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

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This paper explores the design space of elastic buffer (EB) routers by evaluating three representative designs. We propose an enhanced two-stage EB router which maximizes throughput by achieving a 42% reduction in cycle time and 20% reduction in occupied area by using look-ahead routing and replacing the three-slot output EBs in the baseline router of [17] with two-slot EBs. We also propose a singlestage router which merges the two pipeline stages to avoid pipelining overhead. This design reduces zero-load latency by 24% compared to the enhanced two-stage router if both are operated at the same clock frequency; moreover, the single-stage router reduces the required energy per transferred bit and occupied area by 29% and 30% respectively, compared to the enhanced two-stage router. However, the cycle time of the enhanced two-stage router is 26% smaller than that of the single-stage router.

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Section: Related Workmentioning

confidence: 99%

Router designs for elastic buffer on-chip networks

Dally

2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

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“…By using virtual express lanes to connect far apart cores in the network, it is possible to avoid the router overhead at intermediate nodes, and thereby greatly improve NoC performance in terms of power, latency and throughput [4,5]. Performance of NoCs has also been improved by inserting long range wired links following principles of small world graphs [6].…”

Section: Related Workmentioning

confidence: 99%

Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects

Deb

Ganguly

Chang

et al. 2010

ASAP 2010 - 21st IEEE International Conference on Application-Specific Systems, Architectures and Processors

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“…Figure 10a shows the average network latency across the applications for the baseline and SMART NoCs. Compared to the Mesh, SMART reduces network latency by 60.1% on average due to the bypassing of the complete router pipelines 10 . On average, SMART reduces the network latency to 3.8 cycles, which is only 1.5 cycles higher than that of the Dedicated 1-cycle topology.…”

Section: Implementation Tool Flowmentioning

confidence: 99%

“…Examples include Fat Tree [4], StarRing [5], Octegon [2], high-radix crossbar [6], and so on. If coupled with sophisticated link designs such as [7]- [10], these NoCs can realize a single cycle transmission between distant cores. However, this requires knowledge of all applications and their communication graphs at design time to be able to pin these dedicated express links to specific pairs of dedicated cores, and assumes sufficient wiring density to support dedicated links between all communicating cores.…”

Section: Introductionmentioning

confidence: 99%

SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

Chen

Park

Krishna

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cycle Multihop Asynchronous Repeated Traversal (SMART) NoC, a NoC that reconfigures and tailors a generic mesh topology for SoC applications at runtime. The heart of our SMART NoC is a novel low-swing clockless repeated link circuit embedded within the router crossbars, that allows packets to potentially bypass all the way from source to destination core within a single clock cycle, without being latched at any intermediate router. Our clockless repeater link has been proven in silicon in 45nm SOI. Results show that at 2GHz, we can traverse 8 mm within a single cycle, i.e. 8 hops with 1 mm cores. We implement the SMART NoC to layout and show that SMART NoC gives 60% latency savings, and 2.2X power savings compared to a baseline mesh NoC.

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NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication

Cited by 56 publications

References 17 publications

Router designs for elastic buffer on-chip networks

Router designs for elastic buffer on-chip networks

Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects

SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

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