SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

Chen, Chia-Hsin Owen; Park, Sunghyun; Krishna, Tushar; Subramanian, Sandya; Chandrakasan, Anantha P.; Peh, Li-Shiuan

doi:10.7873/date.2013.080

Cited by 63 publications

(39 citation statements)

References 20 publications

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“…This limits latency and throughput savings possible in the context of a multi-hop NoC that requires a more global view of control. For example, using on-demand routing [4], packets can continue to spend multiple cycles in local and global arbitration every time the packet stops short of its destination due to contention.…”

Section: Introductionmentioning

confidence: 99%

“…In this case, each router in the NoC independently arbitrates and routes locally for traversal to adjacent nodes. Recent research proposes to utilize a clockless repeater link to perform more global control and multi-hop traversal [4] to provide dramatic improvements in message latency and network power consumption. However, this previous work still utilizes basic assumptions of on-demand message routing suitable for distributed control even though messages require coalescing of multiple nodes' arbitration and routing.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

MSCS

Kline

Wang

Melhem

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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NoCs (networks-on-chip) are commonly proposed as scalable onchip interconnects for current and future CMPs (chip multi-processors) and many-core systems. While scalable, the lack of global control can create routing inefficiencies detrimental to the overall network latency. Recently, NoCs have been proposed that allow flits to traverse multiple network switches in a single cycle. This requires a more global view of control to allow routers along the path of a packet to configure their switches collectively. In this paper, we propose a reservation based circuit-switching design, MSCS, which provides simplified global control and multi-hop traversal while reducing latency. MSCS performs network control once per network dimension for the lifetime of a packet, while the leading methods require multiple arbitration steps depending on contention in the network. Furthermore, MSCS can perform control for a packet prior to the availability of resources through reservations, while previous schemes only perform control on-demand. Overall, MSCS can reduce the buffer size by 50% over the leading multi-hop scheme while maintaining a nominal latency improvement (1.4%). With the same buffer resources per port, MSCS achieves a 12.7% latency improvement.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

MSCS

Kline

Wang

Melhem

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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“…A test chip at 45nm recently demonstrated that clockless repeated links can go up to 13mm with 1.0V full-swing (16mm with 300mV low-swing) within 1ns [11]. Post-layout simulations of the synthesized SMART control and data paths in 45nm indicate that SSR traversal followed by arbitration limits the speed to 9-11mm/ns [29].…”

Section: Background: Smart Nocmentioning

confidence: 99%

Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs

Kwon

Krishna

Peh

2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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Locality has always been a critical factor in on-chip data placement on CMPs as accessing further-away caches has in the past been more costly than accessing nearby ones. Substantial research on locality-aware designs have thus focused on keeping a copy of the data private. However, this complicates the problem of data tracking and search/invalidation; tracking the state of a line at all on-chip caches at a directory or performing full-chip broadcasts are both non-scalable and extremely expensive solutions. In this paper, we make the case for Locality-Oblivious Cache Organization (LOCO), a CMP cache organization that leverages the on-chip network to create virtual single-cycle paths between distant caches, thus redefining the notion of locality. LOCO is a clustered cache organization, supporting both homogeneous and heterogeneous cluster sizes, and provides near single-cycle accesses to data anywhere within the cluster, just like a private cache. Globally, LOCO dynamically creates a virtual mesh connecting all the clusters, and performs an efficient global data search and migration over this virtual mesh, without having to resort to full-chip broadcasts or perform expensive directory lookups. Trace-driven and full system simulations running SPLASH-2 and PARSEC benchmarks show that LOCO improves application run time by up to 44.5% over baseline private and shared cache.

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“…Link improvement: Low-swing signalling [20] and an asynchronous link [21,22] have been adopted in NoCs to allow multiple-hop traversal in one cycle. Low-swing signalling has poor bandwidth density, and the asynchronous link can have signal skew issues due to interference [23].…”

Section: Noc Router Architecture and Algorithmsmentioning

confidence: 99%

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Agyeman

Zong

Yakovlev

et al. 2017

JLPEA

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Abstract:To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications' execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45% (or 50%) in 3D NoCs (or WiNoCs).

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SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

Cited by 63 publications

References 20 publications

MSCS

MSCS

Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

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